GPDMA hardware block has some requirement regarding the buffers alignments.
Note the previous condition was too permissive. It ignored
source_burst_length during the check of the transaction size.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The Kconfig symbols for selecting HAL content should be part
of the HAL module integration, not defined by the SoC. Split the
symbols between the Series 0/1 Gecko HAL and Series 2 SiSDK HAL
when moving them.
For now, the Series 0/1 HAL symbols retain their name, while new
names consistent with the symbols already defined in the module
integration layer are used for the Series 2 HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
As the number of DMA channels could be different between DMA instances,
get the number from "XDMAC Global Type Register" and validate the
channel used.
Signed-off-by: Tony Han <tony.han@microchip.com>
In case of using HAL_OVERRIDE, avoid clearing the FIFO ERROR flag
before calling the HAL DMA IrqHandler so that the HAL DMA code
handling can be used.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
If hal_override is set, avoid reporting an error and clear the
transfer error (TE) bit so that HAL code can properly handle it.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Support EDMAv3 platform that do not have dmamux or always on capability.
Therefore, memory to memory transfer is limited in this environment.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Co-authored-by: Emilio Benavente <emilio.benavente@nxp.com>
DMA syscalls as they were implemented were unsafe. Accepting a void* was
never acceptable as many things could not be verified about it.
Accepting a channel identifier meant that a user mode thread could
start/stop any DMA channel which in theory could be owned by any other
driver. This shouldn't be possible.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Function stm32_dma_config_channel_function is unused hence remove it
from headers and dma_stm32_v1. In case of dma_stm32_v1, the related
configuration is already part of the LL_DMA_Init call done in
another place in dma_stm32.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The dma_stm32_slot_to_channel function is only applicable on the
STM32Fx series since the LL_DMA_CHANNEL_x macros only exist for those
platforms among the one based on st,stm32-dma-v1.
While checking for !defined(CONFIG_DMAMUX_STM32) is ok to enable this
on STM32Fx, it prevents to disable dmamux on other platforms since
required symbols do not exist.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Convert address for dma when update tcd registers.
- This commit fixes a bug that dma reports source/destination bus errors
when dma try to access the unconveted addresses. The unconverted
addresses will be reserved address from dma view.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Add power management state validation in dw_dma_get_status() to ensure
the device is in active state before attempting to read DMA status.
Returns -EINVAL if device is not active, preventing potential issues
when accessing hardware registers while device is suspended.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Add support for the Renesas RA Direct Memory Access Controller,
including driver source files, Kconfig options, and DTS bindings.
- Add initial implementation of the RA DMAC driver
- Add dedicated Kconfig and CMake integration
- Provide Devicetree bindings for the RA DMAC
- Update module Kconfig to include the new driver
This enables DMA functionality on Renesas RA series MCUs.
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Add a num_of_allocated_channels field to struct dma_mcux_lpc_config. Add
a a capacity check for dma_X_channel_data_arr in dma_mcux_lpc_configure.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
To ease code understanding of offset handling within the driver,
harmonize its treatment within impacted functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32_DMA_STREAM_OFFSET is defined as 0 in case "dma u5" is in use.
Clean up code relating to this define.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
1. Add config and overlay file in test scatter_gather for adp_xc7k_ae350
and adp_xc7k_ae350_clic to support the test case.
2. Modify the config file in test chan_blen_transfer and loop_transfer
because the tests do not support the NOCACHE memory configuration,
the DCACHE configuration needs to be disabled.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
1. Upgrade the ATCDMAC driver to make it compatible with multiple
ATCDMAC series drivers.
2. Rename the driver from ATCDMAC300 to ATCDMACX00.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Change 4e0e3c990d caused
a regression in that SPI_MCUX_FLEXCOMM_TX DMA
transfers weren't properly set to be a peripheral
transfer.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The syntax was wrong for the chosen dtcm node. Also fixing build error
on 1180 by re-allowing the symbol on some tests.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The previous 1ms sleep introduced unnecessary latency
while waiting for the SUSPF flag.
Switching to a 750µs busy-wait provides a more responsive
and precise delay,improving performance in time-sensitive contexts.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
There was actually three different types of configuration modes
happening here, and this function was getting extremely bulky and hard
to read due to the amount of nesting of conditionals. Split these into
separate functions and call them appropriately depending on the type of
transfer.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There is two completely different types of reload modes happening here,
therefore we should split this function into two completely separate
functions because it was getting large and hard to read. Removes
one level of indentation.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Instead of having preprocessor code, make a hidden kconfig
to indicate this and be smarter about the C code (these are all powers
of two)
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The dependency on the chosen node for dtcm can be expressed in Kconfig
language.
Cache we care about is CPU DCACHE, not the meaningless "MCUX Cache"
The macros can be reordered to be simpler by having only one level of
conditional (no nesting) instead of three levels.
Move this code closer in the file to where this cache attribute macro is
actually going to be used (the init macro) instead of randomly splitting
up the struct definitions at the top.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There are multiple bugs related to continuous/circular mode.
Continuous/circular mode is where the DMA runs continuously
until the stop API is called, instead of auto-stopping on
completion on a single transfer. After a stop, the DMA
can then be reconfigured/restarted.
1. Fix bug where stop didn't actually stop. This can cause memory
corruption if the user thought the DMA stopped and repurposed
the dest memory, but in fact the DMA is still writing to it.
The bug was due the incorrect usage of the DMA controller busy
state. The DMA controller is busy only when a transfer is
actively in progress, but the driver needed to stop even if
the transfer is not active but is only enabled (and may become
active on a subsequent trigger event). Change so that data->busy
doesn't use the DMA controller busy state but tracks the enable
state. Also, to make it doubly safe, make stop function always stop
regardless of data->busy state because it is alway safe/correct
to do so.
2. Fix race condition where a stop request from another ISR might race
with a DMA completion interrupt, and the DMA completion callback
gets invoked after the DMA has already been stopped. The fix
is to unregister the callback with the sdk DMA driver, so the
ISR still runs and clear the interrupt without invoking the
callback. There is potentially still a race if the interrupt
is restarted before the ISR fires, so the callback might be
called too early. However, the Zephyr DMA driver doesn't
have the channel level details that the SDK driver does and
it cannot clear just the channel interrupt.
Also a couple of general fixes/improvements:
a. Use interrupt B for end of transfer (single transfer or end
of block list). Use interrupt A for interrupts of a block
in the middle of a transfer or for continuous/circular transfers.
This fixes the dma callback so it can properly report
DMA_STATUS_BLOCK vs DMA_STATUS_COMPLETE.
b. Reorder some fields in struct channel_data to pack a little
better in memory
Signed-off-by: Mike J. Chen <mjchen@google.com>
The dma driver was determining src_inc and dst_inc from the
config of the first block buffer and ignoring the config
flags for any additional buffers in the chain, which could
lead to incorrect transfers (e.g. in a multiple rx buffer
case, if the first buffer was to receive to NULL,
but the subsequent buffers were not NULL, the bug
would manifest as all transfers being made with
dst_inc of 0). Change the driver to setup
each dma descriptor according to the addr_adj flag
of each block_buffer.
Add check that peripheral transfers have addr_adj set to
NO_CHANGE instead of assuming it, to help catch errors.
Also now check for invalid addr_adj request of
decrement, which this controller doesn't support.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The spi_mcux_flexcomm driver uses a special last DMA blk_cfg
to trigger a release of the SPI chip select. This transfer
is always a 4-byte transfer, regardless of the width specified
during dma_configure().
The way the spi_mcux_flexcomm driver communicated this special
transfer was kind of a hack, where the dma_mcux_lpc driver would
assume that when a blk_cfg with source_addr_adj and dest_addr_adj
both set to NO_CHANGE was for this SPI_TX special case.
However, this is an unsafe hack since it is perfectly valid
to have dma use cases for both src/dest_addr_adj to be NO_CHANGE
that is not for SPI_TX. One example is when transmitting a
fixed/repeating value to a periperhal address (e.g. send 100
bytes of the same value from a single memory address over SPI).
This CL introduces a dma_mcux_lpc specific dma channel_direction
which the two drivers now use to cleary request this special
transfer case.
Signed-off-by: Mike J. Chen <mjchen@google.com>
We need to add CONFIG_DMA_MAX_DESCRIPTOR=16 for a lot of tests, then
this default value of this parameter need to be higher. It allows to
delete some overlay files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The LDMA driver currently has a 1:1 mapping between hardware LDMA
descriptors and struct dma_block_config. This patch allows multiple
hardware descriptors to be allocated for a single struct dma_block_config
if the block size exceeds the transfer capacity of a single hardware
LDMA descriptor. This is beneficial for other peripheral drivers: it is
no longer necessary to split the payload by the transfer capacity of a
single hardware LDMA descriptor.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
