Convert the numerous revision compatibles to a DT property for the
revision called nxp,version (inspired from a linux DT property from
st called st,version on their DMA).
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Xilinx AXI DMA Controller is commonly used in FPGA designs.
For example, it is a part of the 1G/2.5G AXI Ethernet subsystem.
This patch adds a driver for the Xilinx AXI DMA that supports
single MM2S and S2MM channels as well as the control and status
streams used by the AXI Ethernet subsystem.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The HAL configuration binding can be done dynamically based on the
IP's address space. The `hal-cfg-index` property is more tied to
software rather than hardware so remove it as an attempt to clean
up the binding.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
In case the LLP wraps we need to re-read the LLPU to make sure we return
the correct value.
Suggested-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Fix DMA driver initialization when PM_DEVICE is set.
Don't put PM policy state lock if it is not active.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
To reduce the latency of CPU accessing/modifying SW TCD content, it
better to put TCD pool to DTCM by default.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Existing dynamic SG mode have some issues which cause uart sync api and
I2S speed test failed.
These issues are: a wrong "Done" bit issue found on UART async api
test. An invalid destination address issue found on I2S speed
test. By introducing loop SG mode, these issues are all fixed.
Some data structures are different between eDMA and eDMA V4, use
different macros defined in SDK driver for each of them.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
- Update GDMA and ADC drivers and remove deprecated entries.
- Rebased hal_espressif to latest bump sync.
- Added ESP Timer and Radio common config values
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Functions related to synchronization inputs and request generators were
present in the DMAMUX driver, despite being completely unused.
Remove them for compatibility with WB0 which lacks this hardware.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
As per dma_stop() documentation, the implementation has to not just stop
the transfer, but also to disable the channel. Before this commit, only
the transfer has been stopped.
Same goes for dma_start(). This also allows the enabling of a channel to
be removed from dma_si32_config().
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Function dma_smartbond_set_channel_status() used incorrect
condition to release state lock.
In initialization function dma_smartbond_init() function
dma_smartbond_set_channel_status() was called for each DMA
channel and tried to release lock that was never taken.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Support multiple instances for dma.
Memset struct data and tcdpool on initialization is not necessary.
Therefore remove it.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
The SMARTDMA is a programmable DMA engine, and supports custom firmware
in order to run complex DMA operations. Update the driver to increase
the flexibility users have when configuring the SMARTDMA with
custom firmware, and remove the RT500 display firmware specific
definitions and functionality from the driver.
This display setup is now handled from the MIPI DSI driver, since the
firmware used for this case is specific to the MIPI DSI IP.
This change also requires an update to the RT500 devicetree, as the
register definition for the SMARTDMA has changed, so the base address
must as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix the DMAMUX driver for the STM32C0 HAL update. Typedef used in function
is now const.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
IRQs are currently only enabled during channel setup
and never disabled. As such, even though they're not
needed (i.e: after a channel has been suspended or stopped)
they remain enabled. Fix this by enabling IRQs during the
channel start() operation and disabling them during the
channel stop() operation.
This change is required by irq chips (i.e: irqsteer) which
perform PM operations during irq_enable()/irq_disable(). If
interrupts are left enabled all the time that means the irq
chip's PM resources might also remain enabled when not needed.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
For DMA channels overridden by HAL DMA, there was no way of
resetting stream busy variable.
Co-authored-by: Maciej Sobkowski <msobkowski@antmicro.com>
Signed-off-by: Dominik Lau <dlau@internships.antmicro.com>
Some comments were not updated following the change in how uncached
memory regions are defined in devicetree.
Signed-off-by: Abderrahmane Jarmouni <git@jarmouni.me>
The STM32 DMA driver can provide interrupts for transfers not yet complete.
However, the current implementation will clear the busy flag for all
interrupts when CONFIG_DMAMUX_STM32 is not enabled. The previous fix for
when CONFIG_DMAMUX_STM32 is enabled should also apply when not enabled.
Also if CONFIG_DMAMUX_STM32 is enabled busy flag will not be cleared when
error interrupts occur.
With this change, the busy flag is only cleared when completion interrupts
in non-cyclic mode or error interrupts occur. These are the cases where
transfer will not continue.
Signed-off-by: Carson Green <cgreen@tuta.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
On some EDMA versions, some TCD registers (e.g: SADDR, DADDR,
SLAST, DLAST, etc...) are extended to 64 bits via adding a new
HIGH register holding the value of bits [63:32]. Since, for now,
the driver doesn't support 64-bit addresses, this scenario is
supported by sign-extending the 32-bit value written to SLAST/DLAST.
SADDR and DADDR are taken care of on HAL side.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Some EDMA versions may have the channel MUX register in the MP
region. To support this scenario, use the `EDMA_HAS_MP_MUX_FLAG`
flag to figure out which channel MUX register to use (TCD or MP).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This supports the minimum of what is required to allow the AES hardware
to be used (memory to peripheral, peripheral to memory).
In addition, to pass some of the existing unit tests, it also supports
memory to memory operators.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
If an overrun happens the user may decide to stop the dma which
unsets the DMA line. Currently, the line is always re-enabled after the
callback.
Switch the order around to fix the problem. Also, always reset the line
even if the user doesn't provide a callback.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
With ACE2/3 the HDA DMA includes registers to read the Linear Link
Position.
Previous platforms (CAVS, ACE1) was able to report the LLP for GPDMA. Since
ACE2 all links are handled with HD-DMA, hence the new register has been
added for the firmware to report the LLP to the host.
Set the total_copied to 0 for older ACE1/CAVS platforms and in case of
host DMA on ACE2/3 since the informatiojn is not available.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT should be set by default
for all Intel ACE platforms
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Remove water mark configuration and handle its interrupt
instead, since it is only present in ESP32S3.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
SOF is designed with the idea that the data transfer
between the host memory and local memory is performed via
DMA. This is not true for imx platform in which the DSP
performs this operation.
Because of the aforementioned design, SOF performs a
cache invalidation operation on the destination memory
region before data is copied further down the pipeline.
For some imx platforms, the destination memory region is
cacheable. As such, some of the data transferred from the
host memory region is held entirely in cache, which means
the RAM and the cache have different data for the same
memory region.
In such cases, performing cache invalidation forces
the DSP to fetch data from RAM instead of the cache, which
means the DSP will read stale data and propagate it further
down the pipeline.
Although not optimal and mostly as a workaround to this issue,
perform a cache WB operation on the destination memory region
to make sure that the cache and the RAM hold the same data.
During the data read operation (to copy it further down the
pipeline) after the aforemention cache invalidation, the DSP
will no longer end up reading stale data.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Previously, configuring the GDMA was limited to a single descriptor,
restricting memory transfers to a maximum of 4kB.
This update introduces support for multiple descriptors, enabling users
to define multiple dma_blocks. The maximum number of descriptors can be
configured via the CONFIG_DMA_ESP32_DESCRIPTOR_NUM option.
Additionally, the dma_get_status() function now reports the index of the
currently processed descriptor
through the status.read_position and status.write_position fields.
Signed-off-by: Armin Kessler <ake@espros.com>
Use LL calls to enable/disable interrupts rather than make calls to the
interrupt controller.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit should deal with fixing
the pending length value returned
upon requesting the status of a channel.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
