This new API allows the assignment of desired DMA channels for
peripheral transfers, enhancing flexibility and control over DMA
operations.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Refactored the driver code to ensure compatibility with the
dma_context API, improving maintainability and consistency
with other DMA drivers in the Zephyr project.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
1. Corrected the burst length processing to be handled in bytes
for the siwx917 DMA drivers.
2. Removed overlay and configuration files associated with the
chan_blen_transfer test application. The chan_blen_transfer
test application attempted to use 8 and 16 byte bursts, which
are not supported by the siwx91x UDMA.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
#84065 replaced diagnostic pragmas with TOOLCHAIN_* macros, but we don't
need to use that here since __used is a cleaner way to indicate that the
function is used and will also prevent it from being optimized away at
link time if LTO is enabled.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Drivers update to use shared interrupt allocator for Xtensa
and RISCV devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for 8-channel configurable DMA controller. The driver
supports the following features:
- memory to peripheral (ch0 to ch5)
- peripheral to memory (ch0 to ch5)
- memory to memory (ch6 and ch7)
Each DMA channel is multiplexed between two or more trigger sources:
- ch0 -> SPI0_TX or UART0_RX
- ch1 -> SPI0_RX or UART0_TX
- ch2 -> LRFD or UART0_TX
- ch3 -> ADC0 or UART0_RX
- ch4 -> AES_A or LRFD
- ch5 -> AES_B or ADC0
- ch6 -> Software Event Channel 0
- ch7 -> Software Event Channel 1
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The TOOLCHAIN_DISABLE_WARNING/TOOLCHAIN_ENABLE_WARNING macros are easier
to read and compiler agnostic.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Some SDMA scripts (e.g multi-fifo) updates the buffer descriptor
count field after a transfer is complete.
Re-initialize the buffer descriptor to point to the correct
transfer size for the next transfer.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
With PDM device NXP HAL uses multi-fifo script. In order
for this script to properly work we need to initialize
multi fifo and SW done configuration.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Add DMA driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This patch adds an initial driver for the WCH DMA
controller. All hardware features and most interface
features are implemented.
Signed-off-by: Paul Wedeck <paulwedeck@gmail.com>
The logic for setting the src_inc and dst_inc would improperly set
these to zero when gatter/scatter was enabled but the respective
gatther_interval/scatter_interval was zero (which would imply
continuous operation).
Fixes: #85403
Signed-off-by: David Leach <david.leach@nxp.com>
-Prefixed Zephyr driver functions with 'siwx917_dma' for consistency
-Added 'siwx917_' prefix to local functions
-Removed inline declaration for param validation functions
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Resolved an issue where application callbacks were not being properly
registered in the DMA driver.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Building with clang warns:
drivers/dma/dma_emul.c:73:20: error: unused function
'dma_emul_xfer_is_error_status' [-Werror,-Wunused-function]
static inline bool dma_emul_xfer_is_error_status(int status)
^
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Implementation of chan_filter and chan_release allows to maintain
synchronization about DMA channel allocation between hal DMA driver and
zephyr DMA driver.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Adds cyclic support, where a multi-block transfer is automatically
reloaded to the first block after the multi-block transfer completes.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Block_ts stores the number of transfers from DMA source, not the
transferred length in bytes.
Regression from 9c4cd3057d.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Implement DMA driver for siwx917 using UDMA peripheral. For now,
Scatter/Gather DMA is not yet supported.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This function allows to not restart DMA engine for driver that gives
new buffer to the DMA engine while a transfer is ongoing.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Improve the silabs ldma driver to support P2M and M2P transfer. It also
adds signal binding to support source request binding in the dts.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The #83556 fixes an error related to DMA initialization which resets
the DMA CRC part. However, the samd/e5x do not have this module inside
DMA controller which causes a compile error. This fixes the issue
checking if the DMAC_CTRL_CRCENABLE macro is defined.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
In the dma loop_transfer test (test_loop_repeated_start_stop()), the
order of calls is dma_config() -> dma_stop() -> dma_start(). This
currently does not work on xmc4xxx because after calling dma_stop(), the
dma would be in a suspended state. Fix this by leaving the suspended state
before exiting dma_stop().
Also don't clear the context (dma_channel->dlr_line and dma_channel->cb)
that was setup by dma_config().
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
When quering the DMA status we need to return the number of pending bytes
left in the transfer. Currently this is inferred by calling
XMC_DMA_CH_GetTransferredData(). However, this function actually returns
the number of items read from the source peripheral (via CTL.BLOCK_TS).
It doesn't guarantee that the last item was fully transferred to the
destination.
When using the ADDR_ADJ_INCREMENT/DECREMENT options it is better to use
DAR register to infer the number of transferred bytes. This points to the
memory address where the next data will be written. It only increments
after the ongoing transfer from source to destination is completed.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Multi channels share one IRQ, add channels-shared-irq-mask on RT1180
attribution to describe the channel shared status, and add code
implementation to register the handler function for each channel
in different interrupts.
Fix legacy building warning issue
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Updated various device definition macros to use the DT_INST variants for
consistency and improved readability.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Fixes issue #83555, where UART transmit operations fail in Zephyr
sysbuild projects using MCUboot and the asynchronous UART API
(`CONFIG_UART_ASYNC_API=y`) on SAM0 devices such as the
ATSAMC21G18A.
The issue occurs because the DMA controller is not reset during
initialization, causing `BASEADDR` and `WRBADDR` registers to retain
MCUboot's configuration. This prevents the application from reconfiguring
these registers to its own RAM addresses, leading to UART transmit
timeouts and triggering the `UART_TX_ABORTED` callback.
This patch resolves the issue by resetting the DMA controller during
initialization in `dma_sam0.c`. The following actions are performed:
- Disables the DMA and CRC modules.
- Applies a software reset to ensure a clean state for reconfiguration.
With this change, UART transmit operations work as expected, improving
stability and compatibility between MCUboot and the application.
Signed-off-by: Tristen Pierson <tpierson@electrohire.com>
Avoid referring to Pico 2 (the name of a board). In this context,
RPI_PICO is used to refer to the (Zephyr) `SOC_FAMILY` rather than the
Pico 1 board. This clarifies common numerical values between the RP2040
and RP2350 SoC series, and enables existing DTS files to be used with
RP2350-based boards with fewer changes.
Remove the use of Zehpyr's `CONFIG_` macros from the device tree files,
and replace them with `SOC_SERIES`-specific files. Update the driver
implementation to conditionally include the correct file. Update
documentation and samples to match.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
This adds initial support for NXP SDMA controller. We make use
of NXP HAL to configure the IP.
SDMA uses BD (buffer descriptors) to describe a transfer. We create
a cyclic list of descriptors and trigger them manually at start and
later when data is available.
This is tested using Sound Open Firmware app on top of Zephyr.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
This commit Modifies the DMA STM32 Kconfig to enable shared IRQ
support for the STM32U0 series.
This change ensures DMA channels with shared IRQs are properly
configured for stm32u0 devices.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
