This patch adds an initial driver for the WCH DMA
controller. All hardware features and most interface
features are implemented.
Signed-off-by: Paul Wedeck <paulwedeck@gmail.com>
The logic for setting the src_inc and dst_inc would improperly set
these to zero when gatter/scatter was enabled but the respective
gatther_interval/scatter_interval was zero (which would imply
continuous operation).
Fixes: #85403
Signed-off-by: David Leach <david.leach@nxp.com>
-Prefixed Zephyr driver functions with 'siwx917_dma' for consistency
-Added 'siwx917_' prefix to local functions
-Removed inline declaration for param validation functions
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Resolved an issue where application callbacks were not being properly
registered in the DMA driver.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Building with clang warns:
drivers/dma/dma_emul.c:73:20: error: unused function
'dma_emul_xfer_is_error_status' [-Werror,-Wunused-function]
static inline bool dma_emul_xfer_is_error_status(int status)
^
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Implementation of chan_filter and chan_release allows to maintain
synchronization about DMA channel allocation between hal DMA driver and
zephyr DMA driver.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Adds cyclic support, where a multi-block transfer is automatically
reloaded to the first block after the multi-block transfer completes.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Block_ts stores the number of transfers from DMA source, not the
transferred length in bytes.
Regression from 9c4cd3057d.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Implement DMA driver for siwx917 using UDMA peripheral. For now,
Scatter/Gather DMA is not yet supported.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This function allows to not restart DMA engine for driver that gives
new buffer to the DMA engine while a transfer is ongoing.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Improve the silabs ldma driver to support P2M and M2P transfer. It also
adds signal binding to support source request binding in the dts.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The #83556 fixes an error related to DMA initialization which resets
the DMA CRC part. However, the samd/e5x do not have this module inside
DMA controller which causes a compile error. This fixes the issue
checking if the DMAC_CTRL_CRCENABLE macro is defined.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
In the dma loop_transfer test (test_loop_repeated_start_stop()), the
order of calls is dma_config() -> dma_stop() -> dma_start(). This
currently does not work on xmc4xxx because after calling dma_stop(), the
dma would be in a suspended state. Fix this by leaving the suspended state
before exiting dma_stop().
Also don't clear the context (dma_channel->dlr_line and dma_channel->cb)
that was setup by dma_config().
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
When quering the DMA status we need to return the number of pending bytes
left in the transfer. Currently this is inferred by calling
XMC_DMA_CH_GetTransferredData(). However, this function actually returns
the number of items read from the source peripheral (via CTL.BLOCK_TS).
It doesn't guarantee that the last item was fully transferred to the
destination.
When using the ADDR_ADJ_INCREMENT/DECREMENT options it is better to use
DAR register to infer the number of transferred bytes. This points to the
memory address where the next data will be written. It only increments
after the ongoing transfer from source to destination is completed.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Multi channels share one IRQ, add channels-shared-irq-mask on RT1180
attribution to describe the channel shared status, and add code
implementation to register the handler function for each channel
in different interrupts.
Fix legacy building warning issue
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Updated various device definition macros to use the DT_INST variants for
consistency and improved readability.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Fixes issue #83555, where UART transmit operations fail in Zephyr
sysbuild projects using MCUboot and the asynchronous UART API
(`CONFIG_UART_ASYNC_API=y`) on SAM0 devices such as the
ATSAMC21G18A.
The issue occurs because the DMA controller is not reset during
initialization, causing `BASEADDR` and `WRBADDR` registers to retain
MCUboot's configuration. This prevents the application from reconfiguring
these registers to its own RAM addresses, leading to UART transmit
timeouts and triggering the `UART_TX_ABORTED` callback.
This patch resolves the issue by resetting the DMA controller during
initialization in `dma_sam0.c`. The following actions are performed:
- Disables the DMA and CRC modules.
- Applies a software reset to ensure a clean state for reconfiguration.
With this change, UART transmit operations work as expected, improving
stability and compatibility between MCUboot and the application.
Signed-off-by: Tristen Pierson <tpierson@electrohire.com>
Avoid referring to Pico 2 (the name of a board). In this context,
RPI_PICO is used to refer to the (Zephyr) `SOC_FAMILY` rather than the
Pico 1 board. This clarifies common numerical values between the RP2040
and RP2350 SoC series, and enables existing DTS files to be used with
RP2350-based boards with fewer changes.
Remove the use of Zehpyr's `CONFIG_` macros from the device tree files,
and replace them with `SOC_SERIES`-specific files. Update the driver
implementation to conditionally include the correct file. Update
documentation and samples to match.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
This adds initial support for NXP SDMA controller. We make use
of NXP HAL to configure the IP.
SDMA uses BD (buffer descriptors) to describe a transfer. We create
a cyclic list of descriptors and trigger them manually at start and
later when data is available.
This is tested using Sound Open Firmware app on top of Zephyr.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
This commit Modifies the DMA STM32 Kconfig to enable shared IRQ
support for the STM32U0 series.
This change ensures DMA channels with shared IRQs are properly
configured for stm32u0 devices.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Make sure that channels are inactive before releasing them.
This way, there won't be any leftover interrupts needed to be
handled when disabling IRQs.
This patch introduces a new state: CHAN_STATE_RELEASING. This is mostly
useful for the per-channel PD support in which the ISR needs to check
that the channel PD is enabled before attempting to access its register
space.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Commit 48b98a9284 ("drivers: dma: dma_nxp_edma: disable IRQs when
not needed") moved the IRQ enable operation to edma_start() and added
an IRQ disable operation in edma_stop(). This is wrong because it breaks
the DMA API contract w.r.t dma_start() being `isr-ok` on imx8qm/imx8qxp.
As such, move the IRQ enable and disable operations in
dma_request_channel() and dma_release_channel().
Note1: managing the interrupts like this is only really needed when
dealing with interrupt controllers that have a power domain associated
with it (which is the case for irqstr on imx8qm/imx8qxp).
Note2: Zephyr has no reference count for shared interrupts so disabling
a shared interrupt without checking if someone else is using it is
dangerous.
Based on the aforementioned notes, the irq_disable() operation is only
performed if irqstr is used as an interrupt controller (which is only
the case for imx8qm/imx8qxp). Otherwise, the operation isn't needed.
Fixes#80573.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The channel state transitions are currently performed at the
beginning of each of the functions that triggers them
(e.g: edma_start(), edma_stop(), etc...). The main issue with
this approach is the fact if there's any failures after the state
transition then the channel will be in the target state without
performing the required steps for it.
For instance, during edma_config(), if any of the functions after
the state transition (the channel_change_state() call) fails
(e.g: get_transfer_type()) fails then the state of the channel
will be CONFIGURED even if not all the required steps were performed
(e.g: setting the MUX, configuring the transfer, etc...).
To fix this, split the state transition into two steps:
1) Check if the transition is possible.
2) Do the transition.
First step should be done before any configurations to make sure
that we should be performing them in the first place, while the
second step should be performed after all configurations, thus
guaranteeing that all the required steps for the target state were
performed before transitioning to it.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This patch refactors the power management initialization for the Intel
ADSP GPDMA driver. The changes include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `intel_adsp_gpdma_init`
function.
2. Ensuring that the GPDMA driver is initialized with the appropriate
power management state and that runtime power management is
automatically enabled based on the device tree configuration.
These changes streamline the power management initialization process and
ensure consistency with other drivers.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses the issue of invalid initialization sequence and
the use of registers in `dma_config` before the device is fully
initialized in the Intel ADSP HDA DMA driver.
Changes include:
1. Moving the `intel_adsp_hda_channels_init` call to the
`intel_adsp_hda_dma_init` function to ensure that channels are
initialized during device initialization.
2. Removing the redundant call to `intel_adsp_hda_channels_init` from
the `PM_DEVICE_ACTION_RESUME` case in the
`intel_adsp_hda_dma_pm_action` function.
These changes ensure that the device and its channels are properly
initialized before any DMA configuration is performed, preventing access
to hardware registers before the device is ready.
**Note:** This is a proposed solution, and a different approach should
be considered. Currently, we are accessing registers before the device
and power domain are fully powered up. This solution likely works
because the DMA is used to load firmware during the boot process, and
the necessary power domains are already powered up. Further
investigation and a more robust solution are recommended to ensure
proper initialization and power management.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses several issues with the Intel ADSP HDA DMA driver:
1. Refactors the HDA DMA power management initialization. The previous
use of `pm_device_runtime_enable` was incorrect. The updated approach
relies on enabling runtime power management through the device tree
using the `zephyr,pm-device-runtime-auto` property. Additionally, the
patch removes redundant device initialization steps as these are already
handled by `pm_device_driver_init` when the device is under a power
domain.
2. Corrects the power domain assignment for the HDA link. The HDA link
was previously assigned to the io0 power domain based on a
misinterpretation of the documentation. The correct power domain
assignment is now based on updated documentation for LNL, ensuring that
the HDA link is associated with the appropriate power domain.
These changes ensure that the HDA DMA driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the correct power domains are used.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
New HAL update changed the prototype of the check DMA flag functions.
H7 and U0 use a const parameter for these functions.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
From the API documentation, `dma_api_chan_filter`` can be given a value
of NULL for `filter_param`. Match the behaviour of most implementations,
and return true. This removes misleading error messages logged during
tests (e.g. `test_tst_dma0_m2m_loop`).
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Enumerate explicitly on which SoC's DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT
should be set by default. For new platforms in the ACE series, the
default should be disabled.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Use the existing 'atomic' bitmask to speed up ISR processing for
CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT. This bitmask is used
to track enabled DMA channels.
In the common case, only a few DMA channels are active and low
channels are allocated first. Take advantage of this and not
iterate over all DMA channels of all all host devices. Rather
break out as soon as L1 exit handling is done for all enabled
channels.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
