Corrects an incorrect transfer size calculation when setting up DMA
transfers with a data size other than one byte.
Signed-off-by: John Batch <john.batch@infineon.com>
* Corrects DMA length calculation when data size is not one byte.
* Corrects incorrect descriptor address assignment in chain operations.
Signed-off-by: John Batch <john.batch@infineon.com>
`edma_reload_loop` doesn't take into account the DMA possible channel
gap. This is an issue for S32K3 series leading to system crashes when
higher DMA channels are used.
Signed-off-by: Razvan Heghedus <razvan.heghedus@protonmail.com>
The Pico SDK expects a transfer count (items), not a byte count. The
driver incorrectly passed the byte size, causing buffer overflows on
16-bit and 32-bit transfers.Fix this by storing the transfer width in
the channel configuration and dividing the block size by that width
to calculate the correct transfer count.
Fixes#99435
Signed-off-by: Ashirwad Paswan <ashi06712@gmail.com>
Move the descriptor storage into the per-instance data structure rather
than being global, as they should not be shared between instances.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The way the driver was storing IRQ numbers for later use in the various
locking modes was not correct, causing the wrong IRQs to potentially be
disabled/enabled in some modes. Refactor the way this is done to be
cleaner, and also the way the different locking modes are implemented in
order to ensure that all modes receive compile test coverage.
Also, ensure that the IRQ for the RX or TX channel is always disabled
during the execution of the corresponding ISR, to prevent it from being
preempted by itself if the DMA core raises another interrupt during the
ISR execution.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This driver has a config option
DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS to allow
it to be used on platforms where DMA memory access is not automatically
cache coherent. However, fully disabling the dcache when accessing DMA
buffers/descriptors is not necessary and is potentially problematic.
This can be handled more selectively by doing explicit cache invalidate
and/or flush operations on the buffers involved as required.
Note that this does introduce a requirement that RX DMA buffers provided
to the driver are cache line aligned, as otherwise the required cache
invalidate operation could potentially corrupt unrelated data. This is
explicitly checked when a DMA RX operation is started.
Tested on Cortex-R5 with data cache enabled.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The driver previously had a timer to periodically check for completed
TX/RX transfers in case an interrupt notification was missed. With
previous changes to the driver to avoid lost interrupt wakeups, this
workaround should no longer be required, so remove it.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Fix some issues in the driver's DMA interrupt handling:
-Ensure that interrupts are cleared prior to handling interrupt events,
so that events raised during interrupt processing will cause the
hardware to raise a new interrupt
-Ensure that we do not overwrite existing DMA descriptors which are
incomplete (such as by trying to execute more transfers than there are
slots in the descriptor ring)
-Ensure that error events reported by the DMA engine are reported
-Rename some of the variables to track pending and completed ring
locations for better clarity
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Doing a reset of the DMA engine during the dma_configure operation is
problematic when using the DMA core in combination with the Xilinx AXI
Ethernet core, since the DMA core's reset signals are normally
propagated into the Ethernet core. This means that after the Ethernet
core initializes and starts a DMA operation for the first time, the DMA
core is reset, wiping out all of the register settings that the Ethernet
core has made.
To avoid this, move the DMA core reset and other initialization which
only needs to be done once into the init function, so this is done
during initial driver load and not deferred until later.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Instead of using a packed structure to define the register map, just
create an enum for the registers and use that to refer to them. This
avoids the need for repeatedly disabling GCC warnings for taking the
address of packed structure members.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS
option is not meaningful to enable unless the platform/configuration
actually supports the corresponding cache maintenance operations. Add
dependencies accordingly.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Update EDMA device tree nodes for NXP MCXE31B platforms to align
with the unified EDMA driver implementation.
Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
The DMA_MCUX_EDMA_V5 configuration option has been removed and replaced
with DMA_MCUX_EDMA_V4, as both versions share the same register layout
and can use the same driver implementation.
Key changes:
- Remove CONFIG_DMA_MCUX_EDMA_V5 Kconfig option
- Replace DMA_MCUX_EDMA_V5 conditionals with DMA_MCUX_EDMA_V4
- Remove DMAx_Type typedef, use DMA_Type directly
- Update EDMA_HW_TCD macros for V4 to use HAL-provided accessor macros
- Add DMA_MCUX_EDMA_DMAMUX Kconfig option to control DMAMUX support
based on device tree property
- Update device tree binding to add has-dmamux property
- Update HAL driver selection to use DMA_MCUX_EDMA_DMAMUX instead of
DMA_MCUX_EDMA for DMAMUX component
- Add SOC_SERIES_MCXE31X to DMA_MCUX_TEST_SLOT_START configuration
- Calculate DMA_TCD_ALIGN_SIZE from edma_tcd_t structure size
Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
stm32h7rsxx bumps to STM32CubeH7RS version 1.3.0.
stm32l4xx bumps to STM32CubeL4 version 1.18.2.
stm32l5xx bumps to STM32CubeL5 version 1.6.0.
stm32n6xx bumps to STM32CubeN6 version 1.3.0.
Update dma_stm32.h to sync with HAL new function prototype for
LL_DMA_IsActiveFlag_HT*() functions that now expect a const pointer
on STM32L4X series. While at it, also update the STM32MP13X series
that expects the same prototypes.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Refactor IRQ handler to set status variable in each branch and invoke
the callback once at the end, reducing code duplication.
Add null check for `dma_callback` in dma_stm32u5.c to match with
dma_stm32.c pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Refactor IRQ handler to set status variable in each branch and invoke
the callback once at the end, reducing code duplication.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Commit e7f222a fixed the bug where a data size mismatch produces unexpected
behavior with the DMA on V1 devices. However, this limitation is only valid
for the STM32 series with V1 DMA, V2 doesn't have this. The STM32CubeMX
configuration tool correctly implements this limitation in the UI,
it is a good way to cross-check.
Signed-off-by: Benedek Kupper <kupper.benedek@gmail.com>
Call pm_policy_device_power_lock_put/pm_policy_device_power_lock_get
to coordinate with system level power modes.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Drop cat1 from the binding files to enable reuse by other
category devices as well.
Fixes#99174
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit introduces a new DMA driver for NXP platforms,
specifically supporting the MCXC/kinetis series.
Please access https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true
to download MCXC44x Sub-Family Reference Manual for more details.
DMAMUX can be found in Chapter 20 and DMA in Chapter 21.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Enable clock control by default for siwx91x SoCs. Moreover, most
drivers for siwx91x soc depend on clock control, but didn't declare
it.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This patch fix a reg write that needs to be done before calling the
callback. Since the user can start a new dma transfer in the callback,
it can miss the interrupt from the new transfer if the new transfer is
done before the interrupt bit is cleared.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Removed unnecessary power management state lock calls since the DMA is
on a power domain that already handles state locking.
It will now managed directly pm_device which will active power_domain
and then block pm_state.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The source and destination burst lengths can be configured with a value
from 1 to 64. As the appropriate values are available in the DMA
configuration structure provided by Zephyr, these can be set during driver
configuration. Unfortunately, the STM32 DMA LL API does currently not
provide the minimum and maximum values.
Signed-off-by: Pascal Linder <pascal.linder@zuehlke.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix the STM32 DMA driver did not check if the optional dma_callback was
set in dma_stm32_configure(). This could lead to a hard fault when an
interrupt occurs and the callback is NULL, even though the API allows
the callback to be omitted.
Fixes#97454
Signed-off-by: Wenxi Xu <xuwenxi0517@gmail.com>
GPDMA does not support DMA_ADDR_ADJ_NO_CHANGE with a memory buffer. This
feature is required fro the SPI driver. Hopefully, SPI driver is the only
user of this feature.
Therefore, this commit introduces a hack for SPI. When the user want to
ignore the Rx data (= when he pass a NULL pointer for the Rx buffer),
rather than overwriting the destination in a loop, we just disable the rx
DMA.
This introduce a limitation: since Rx DMA stop early, any following Rx
request will start earlier than expected. Therefore, this patch breaks
cases with interleaved Rx buffers. In other words, the NULL buffer must be
the last one.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
GPDMA does not support DMA_ADDR_ADJ_NO_CHANGE with a memory buffer. This
feature is required for the SPI driver. Hopefully, SPI driver is the only
user of this feature.
Therefore, this commit introduces a hack for SPI. When the user request an
Rx transaction, rather than copying content of mosi_overrun parameter, it
configures the DMA to fill the destination memory (with either 0s or 1s).
Obviously, this only works if mosi_overrun is 0x00 or 0xFF. Hopefully, none
will need any other value.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Since the single-linked list management is well localized, the variable
names can now be abbreviated a bit.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The management of the single-linked list was made in various places:
- RSI_GPDMA_BuildDescriptors()
- after sys_mem_blocks_alloc()
- at the end of the loop
Centralize it at the end of the loop.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Improve the STM32 DMA driver to only enable transfer and half-transfer
interrupts if the interrupt handler has effects beside clearing the
isr flag. This improves system performance as unnecessary interrupts
are no longer raised by the hardware.
Signed-off-by: Axel Utech <utech@sofiha.de>
