Add support for the Renesas RA Direct Memory Access Controller,
including driver source files, Kconfig options, and DTS bindings.
- Add initial implementation of the RA DMAC driver
- Add dedicated Kconfig and CMake integration
- Provide Devicetree bindings for the RA DMAC
- Update module Kconfig to include the new driver
This enables DMA functionality on Renesas RA series MCUs.
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Add a num_of_allocated_channels field to struct dma_mcux_lpc_config. Add
a a capacity check for dma_X_channel_data_arr in dma_mcux_lpc_configure.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
To ease code understanding of offset handling within the driver,
harmonize its treatment within impacted functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32_DMA_STREAM_OFFSET is defined as 0 in case "dma u5" is in use.
Clean up code relating to this define.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
1. Add config and overlay file in test scatter_gather for adp_xc7k_ae350
and adp_xc7k_ae350_clic to support the test case.
2. Modify the config file in test chan_blen_transfer and loop_transfer
because the tests do not support the NOCACHE memory configuration,
the DCACHE configuration needs to be disabled.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
1. Upgrade the ATCDMAC driver to make it compatible with multiple
ATCDMAC series drivers.
2. Rename the driver from ATCDMAC300 to ATCDMACX00.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Change 4e0e3c990d caused
a regression in that SPI_MCUX_FLEXCOMM_TX DMA
transfers weren't properly set to be a peripheral
transfer.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The syntax was wrong for the chosen dtcm node. Also fixing build error
on 1180 by re-allowing the symbol on some tests.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The previous 1ms sleep introduced unnecessary latency
while waiting for the SUSPF flag.
Switching to a 750µs busy-wait provides a more responsive
and precise delay,improving performance in time-sensitive contexts.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
There was actually three different types of configuration modes
happening here, and this function was getting extremely bulky and hard
to read due to the amount of nesting of conditionals. Split these into
separate functions and call them appropriately depending on the type of
transfer.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There is two completely different types of reload modes happening here,
therefore we should split this function into two completely separate
functions because it was getting large and hard to read. Removes
one level of indentation.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Instead of having preprocessor code, make a hidden kconfig
to indicate this and be smarter about the C code (these are all powers
of two)
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The dependency on the chosen node for dtcm can be expressed in Kconfig
language.
Cache we care about is CPU DCACHE, not the meaningless "MCUX Cache"
The macros can be reordered to be simpler by having only one level of
conditional (no nesting) instead of three levels.
Move this code closer in the file to where this cache attribute macro is
actually going to be used (the init macro) instead of randomly splitting
up the struct definitions at the top.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There are multiple bugs related to continuous/circular mode.
Continuous/circular mode is where the DMA runs continuously
until the stop API is called, instead of auto-stopping on
completion on a single transfer. After a stop, the DMA
can then be reconfigured/restarted.
1. Fix bug where stop didn't actually stop. This can cause memory
corruption if the user thought the DMA stopped and repurposed
the dest memory, but in fact the DMA is still writing to it.
The bug was due the incorrect usage of the DMA controller busy
state. The DMA controller is busy only when a transfer is
actively in progress, but the driver needed to stop even if
the transfer is not active but is only enabled (and may become
active on a subsequent trigger event). Change so that data->busy
doesn't use the DMA controller busy state but tracks the enable
state. Also, to make it doubly safe, make stop function always stop
regardless of data->busy state because it is alway safe/correct
to do so.
2. Fix race condition where a stop request from another ISR might race
with a DMA completion interrupt, and the DMA completion callback
gets invoked after the DMA has already been stopped. The fix
is to unregister the callback with the sdk DMA driver, so the
ISR still runs and clear the interrupt without invoking the
callback. There is potentially still a race if the interrupt
is restarted before the ISR fires, so the callback might be
called too early. However, the Zephyr DMA driver doesn't
have the channel level details that the SDK driver does and
it cannot clear just the channel interrupt.
Also a couple of general fixes/improvements:
a. Use interrupt B for end of transfer (single transfer or end
of block list). Use interrupt A for interrupts of a block
in the middle of a transfer or for continuous/circular transfers.
This fixes the dma callback so it can properly report
DMA_STATUS_BLOCK vs DMA_STATUS_COMPLETE.
b. Reorder some fields in struct channel_data to pack a little
better in memory
Signed-off-by: Mike J. Chen <mjchen@google.com>
The dma driver was determining src_inc and dst_inc from the
config of the first block buffer and ignoring the config
flags for any additional buffers in the chain, which could
lead to incorrect transfers (e.g. in a multiple rx buffer
case, if the first buffer was to receive to NULL,
but the subsequent buffers were not NULL, the bug
would manifest as all transfers being made with
dst_inc of 0). Change the driver to setup
each dma descriptor according to the addr_adj flag
of each block_buffer.
Add check that peripheral transfers have addr_adj set to
NO_CHANGE instead of assuming it, to help catch errors.
Also now check for invalid addr_adj request of
decrement, which this controller doesn't support.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The spi_mcux_flexcomm driver uses a special last DMA blk_cfg
to trigger a release of the SPI chip select. This transfer
is always a 4-byte transfer, regardless of the width specified
during dma_configure().
The way the spi_mcux_flexcomm driver communicated this special
transfer was kind of a hack, where the dma_mcux_lpc driver would
assume that when a blk_cfg with source_addr_adj and dest_addr_adj
both set to NO_CHANGE was for this SPI_TX special case.
However, this is an unsafe hack since it is perfectly valid
to have dma use cases for both src/dest_addr_adj to be NO_CHANGE
that is not for SPI_TX. One example is when transmitting a
fixed/repeating value to a periperhal address (e.g. send 100
bytes of the same value from a single memory address over SPI).
This CL introduces a dma_mcux_lpc specific dma channel_direction
which the two drivers now use to cleary request this special
transfer case.
Signed-off-by: Mike J. Chen <mjchen@google.com>
We need to add CONFIG_DMA_MAX_DESCRIPTOR=16 for a lot of tests, then
this default value of this parameter need to be higher. It allows to
delete some overlay files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The LDMA driver currently has a 1:1 mapping between hardware LDMA
descriptors and struct dma_block_config. This patch allows multiple
hardware descriptors to be allocated for a single struct dma_block_config
if the block size exceeds the transfer capacity of a single hardware
LDMA descriptor. This is beneficial for other peripheral drivers: it is
no longer necessary to split the payload by the transfer capacity of a
single hardware LDMA descriptor.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Introduce the ACE 4.0 architecture, along with support for the NVL and
NVL-S platforms within the Intel ADSP framework in the Zephyr project.
This update includes:
- Addition of ACE 4.0 architecture configurations in Kconfig and
Kconfig.intel_adsp.
- Inclusion of device tree source files for NVL and NVL-S platforms,
defining CPU, memory, and peripheral configurations.
- Updates to driver files to support ACE 4.0 specific features,
including DMIC and SSP configurations.
- Introduction of new header files for ACE 4.0, detailing boot,
interrupt, IPC, power, and shim functionalities.
- Modifications to the CMakeLists.txt to include ACE 4.0 MMU support.
- Addition of default configurations for NVL and NVL-S platforms in
Kconfig.defconfig.ace40.
The NVL and NVL-S platforms are part of the Nova Lake series, targeting
advanced audio processing capabilities. ACE 4.0 introduces enhanced DSP
capabilities and advanced power management features, improving audio
stream handling and synchronization compared to ACE 3.0.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Create Kconfig variable NXP_INPUTMUX, which selects the fsl_inputmux
driver. Imply the MCUX component symbol from it. Imply that variable
from the NXP PINT, SmartDMA and LPC DMA drivers and from the mimxrt685s
SoC.
This needed to be done for the mimxrt700_evk/mimxrt798s/hifi4 domain, as
the INPUTMUX peripheral handles IRQ assginments and its driver
(fsl_inputmux) is used directly by the domain's soc.c. Instantiating the
currently dependent drivers (for PINT and SmartDMA) isn's possible nor
reasonable on the said target.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
There is really no need for this header file at all besides if
there is a requirement to be annoying.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The transfer must be aborted before clearing the status flags otherwise
they will be set again before the transfer is aborted and stay set
causing infinite interrupt.
Also, elevate the log message to error level and give it actual useful
information. The "flag" being logged before literally just is a bit that
says if there is an error or not, which we already know by virtue of
handling an error. The channel error status has actual details about
what was the reason of the error. Also this status should be reported
before the transfer is aborted to get the right status.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
1. The edma version 5 share one driver with edma 4.
2. Edma5 tcd structure some difference, Use tcd type to distinguish,
and Edma5 uses 64 bytes for alignment instead of 32.
3. Some platforms have some address offsets for certain memory
when processing from a DMA perspective, such as imx95 cm7 TCM,
so add offset processing.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
XCACHE has been designed for RT700, tcd pool need to be put in
noncache region, update driver to support
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
we iterate over all the channels, and if more than one channel is
active at a time. interrupt on any one of active channel was
triggering callback for other active channel, because flags value
is 1 (enabled). this is commit handle this behaviour and only
trigger callback if bits other than status is set
Signed-off-by: Anuj Pathak <anuj@croxel.com>
The SDK FSL DMA driver converts descriptor addresses to DMA's address
space when linking descriptors. The Zephyr dma_mcux_lpc driver is
missing the inverse conversion when dereferencing the linked next
descriptor pointer.
This isn't a problem when this driver is used on the M33 core
of the MIMXRT595S because the M33 can access the address space
of the DMA (0x20000000+). But when the Fusion F1 DSP core uses
this driver, the DSP cannot access the DMA's address space
so the inverse conversion is needed.
Signed-off-by: Yicheng Li <yichengli@google.com>
The driver treats the `source_data_size` and `dest_data_size` as a
width in bits and converts 8 bits to 1, 16 bits to 2, and 32 bits to 3.
This should be a width in bytes with 1 byte mapping to 0, 2 bytes to
1, and 4 bytes to 3.
Note that this preserves the current behaviour of silently accepting
invalid transfer bit widths.
Signed-off-by: Michael Hope <michaelh@juju.nz>
For MAX32657, 'MXC_DMA_EnableInt' function requires DMA instance
and this causes build error. To fix this, created wrapper version
of this function and update driver with it.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
The typical way of calling INPUTMUX_AttachSignal() is to
bracket it around INPUTMUX_Init() and INPUTMUX_Deinit()
calls because we can reduce power consumption by not
keeping the interface powered when not changing INPUTMUX.
This driver was violating that convention, which caused
it to not coexist well with other code that followed the
usage convention because the INPUTMUX might be initialized
or not depending on execution order with the other modules.
Signed-off-by: Mike J. Chen <mjchen@google.com>
DMA channel stats like pending_length or free is not protected
and can be modified in parallel by a consumer and a producer.
This can result in non-atomic updates which in turn will result
in using stale data.
Fix this by making regions of code accessing dma stats atomic.
Fixes: e94c86f395 ("drivers: dma: Add initial support for NXP SDMA")
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Each time we configure an SDMA channel we also compute the total
allocated DMA buffer length but we assume is initialized with zero.
This is true each time a channel is requested. But if there are
multiple calls to configure without releasing the channel the buffer
length is not correctly computed.
So, we need to initialize it with zero each time we reconfigure the dma
channel.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Add the PM handler. Reinitialize the DMA block in the
TURN_ON action, this is needed for some SoC's after the system
exits certain power modes.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Commit fa4a9db7a3 ("dma: intel_adsp_hda: Fix invalid init sequence and
register use") moved intel_adsp_hda_channels_init() out from resume
path. This causes a regression to CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT
as without irq_config() call the interrupt configuration may be partial.
Address this by calling irq_config() unconditionally on resume path.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Current DMA driver reload function only works for 8-bit
data. This is due to incorrect interpretation of size
argument. Added changes to support other xfer sizes.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
