When a DMA channel is routed through the channel mux (dma_slot != 0), each
minor loop is paced by the peripheral request signal. In this case, the
caller-chosen burst length must be preserved to ensure correct operation.
Previously, the driver would collapse the minor loop into the whole block
for all memory-to-memory transfers without source chaining, but this logic
should only apply to genuine software-triggered transfers. Peripheral-
triggered transfers (e.g., FlexIO LCDIF) expect one minor loop per shifter
round, and collapsing the loop breaks this requirement.
Add a check for dma_slot == 0 to ensure burst length collapsing only occurs
for software-triggered transfers, not peripheral-triggered ones.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Replace direct esp_cache_msync() calls in the ESP32 GDMA and
SPI master drivers with the portable sys_cache_data_*() API.
Zephyr's API is a compile-time no-op when CACHE_MANAGEMENT is
disabled, so the same source compiles cleanly on every ESP32
SoC and stays cost-free where there is no writeback cache.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds support for no increment needed to support the LPSPI and other
peripherals with a FIFO buffer.
Furthermore we disable interrupts on each major loop on SG, instead
only do an interrupt on the final TCD.
Also a small optimization in dma_mcux_edma_reset_channel, where TCD
got zeroed twice.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The GDMA_LL_AHB_TX_RX_SHARE_INTERRUPT macro used to gate the
shared rx/tx interrupt handler is no longer defined in the HAL,
so the guard always evaluates false and breaks the IRQ wiring
on ESP32-C2 and ESP32-C3.
Replace it with a check derived from devicetree that compares
the declared interrupt count against the channel pair count.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add realtek ameba dma driver.
Signed-off-by: minyuan xue <minyuan_xue@realsil.com.cn>
drivers: dma: ameba: use IF_ENABLED instead of COND_CODE_1 with empty else
Replace COND_CODE_1(CONFIG_DMA_AMEBA_LLI, (...), ()) with the cleaner
IF_ENABLED(CONFIG_DMA_AMEBA_LLI, (...)) idiom in the DMA_AMEBA_INIT
macro. The two forms are semantically identical; IF_ENABLED avoids the
superfluous empty else argument.
Signed-off-by: minyuan xue <minyuan_xue@realsil.com.cn>
DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS describes
a specific implementation strategy rather than the underlying intent:
manage cache coherency manually because the platform doesn't provide
hardware coherency for DMA accesses. Tying the symbol name to the
mechanism makes it harder to evolve the driver to a different coherency
strategy without breaking existing user configurations.
Introduce DMA_XILINX_AXI_DMA_MANUAL_CACHE_COHERENCY with the same
semantics and update the driver's #ifdef sites to use it. Keep the
original symbol around as an invisible alias that selects DEPRECATED
and the new symbol so existing out-of-tree configs continue to work
and produce a deprecation warning at build time instead of silently
losing the behaviour.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
The Xilinx PG021 spec requires the DMA to clear DMACR.RESET before any
further DMACR writes are honored. Use Zephyr's WAIT_FOR() helper from
<zephyr/sys/util.h> to spin on DMACR.RESET clearing after the soft-reset
write, with an XILINX_AXI_DMA_RESET_TIMEOUT_MS ceiling. On timeout, log
an error and return -EIO so the failure surfaces immediately instead of
being absorbed by silently dropped subsequent register writes.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
The IRQ lock/unlock helpers used bare 0x1 / 0x2 bit literals in the lock
key returned to the caller, and indexed the per-channel array with bare
0 and 1. Both required a "TX is 0, RX is 1" comment to read.
Replace the bit literals with named constants
XILINX_AXI_DMA_LOCK_KEY_TX_ENABLED / _RX_ENABLED, derived from the
existing channel index defines via BIT(), and replace the bare channel
indices with XILINX_AXI_DMA_TX_CHANNEL_NUM / _RX_CHANNEL_NUM. The
"TX/RX is N" / "TX/RX was enabled" comments become redundant and are
removed.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Add DMA driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Memory to Memory transfer
- Peripheral to Memory transfer
- Memory to Peripheral transfer
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Fix two issues in DMA driver:
1. ISR was invoking callback for all interrupts including suspend.
Add check to invoke callback only for transfer complete (TCMPL)
or transfer error (TERR) interrupts.
2. dma_get_status returned stale pending_length after config/reload
because write-back descriptor was not synced with base descriptor.
Sync write-back in dma_mchp_config and dmac_desc_reload_block.
Also improve type safety by changing void* to dmac_descriptor_registers_t*
in descriptor setup functions.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Enable the optional clock described in devicetree during eDMA
driver initialization.
Keep RT7xx request-enable programming in board init so this
branch only moves the clock-control portion into the driver.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add optional devicetree reset support to the MCUX eDMA
driver and deassert the reset line during initialization
when a reset specifier is provided.
Boards which do not describe a reset remain unchanged.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Introduces SYS_MEM_BLOCKS_DEFINE_TYPE() and
SYS_MEM_BLOCKS_DEFINE_STATIC_TYPE() helpers to allow the user to declare
mem blocks without having to manually ensure the alignment is correct,
which was very error-prone.
Matches the new K_MEM_SLAB_DEFINE_TYPE.
Signed-off-by: Egill Sigurdur <egill@egill.xyz>
Introduces K_MEM_SLAB_DEFINE_TYPE() and K_MEM_SLAB_DEFINE_STATIC_TYPE()
helpers to allow the user to declare slabs for types without having to
manually ensure the alignment is correct.
Manual slab alignment was very error-prone and this change fixes several
instances of misalignment that would be trapped by the undefined
behavior sanitizer when running on 64-bit targets.
Signed-off-by: Egill Sigurdur <egill@egill.xyz>
Don't clear DMA status flags when DMA controller is managed by the HAL.
The same logic was introduced in the dmav1/dmav2 driver by commit
110c61bfea.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
There is a typo in the DT_INST_IRQ_ macro. SDMA was used
until now only with HIFI4 DSP (xtensa) and for this arch
priority parameter is ignored.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Add DMA drivers for AMD ACP 7.0 audio DSP:
- Host DMA driver for memory transfers between system memory
and ACP audio processing units
- SoundWire DMA driver for audio streaming over SoundWire bus
Signed-off-by: Siva Subramanian Ravi Saravanan <sravisar@amd.com>
Rename BL61x GPIO and pinctrl drivers to bl61x_808 variants since
BL808 shares identical register layouts. Update compatible strings,
Kconfig, CMakeLists, and BL61x device tree accordingly. Extend the
DMA and IR receiver drivers' BL61x guards to also cover BL808.
Signed-off-by: William Markezana <william.markezana@gmail.com>
SF32LB DMA cleared its software busy bit on half-complete.
The QSPI NOR write path polled that bit while holding the flash lock.
Clear the DMA status bit only on completion or error.
Derive busy from the active state plus pending_length.
Poll pending_length until the flash DMA transfer reaches zero.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
The driver never enabled the transfer error interrupt. If a transfer error
occurred, the ISR would not be called which could result in a deadlock.
Make sure the transfer error interrupt is enabled.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Wire the Kinetis LMEM-capable SoCs into the generic cache
management path by selecting the LMEM driver, enabling the
available instruction and system-bus cache capabilities, and
defaulting these parts to CACHE_MANAGEMENT with the external
cache backend.
Keep MCUX eDMA descriptors in the default SRAM placement on
SYSMPU-based Kinetis parts. Their SRAM region remains outside
the cached LMEM area, so they do not use the generic
NOCACHE_MEMORY path.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Extend the ESP32 GDMA driver to support ESP32-C5. Add the C5 SoC to
the AHB GDMA configuration and define the per-channel interrupt
source mappings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
stm32wbxx bump to version to 1.24.0
stm32wlxx bump to version 1.4.0
Update dma_stm32.h to sync with HAL new function prototype for
LL_DMA_IsActiveFlag_HT*() functions that now expect a const pointer
on STM32WLX series.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Set DMA_TCD_QUEUE_SIZE default to 4 when I2S_MCUX_SAI is enabled.
The MCUX SAI driver preloads 3 RX DMA blocks and requires the TCD
queue size to be greater than 3 to satisfy its BUILD_ASSERT and avoid
build failures in MCUX SAI I2S configurations.
Fixes#103997
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a loop to triggerchannel start for each remaining major loop iteration
to ensure complete data transfer.
Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
Add a new DMA driver for the Infineon DMAC (Direct Memory Access
Controller) specifically for PSoC4 Series.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Adding a way to configure x-loop increments greater than 1.
Fixing an issue where DMA descriptors that were allocated from a shared
pool were never freed.
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
Modifying DMA configuration to be more specific about when to use
software triggeres and the single elmeent input trigger type.
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Correct GET_EDMA_CHANNEL_SHARED_IRQ_MASK_WIDTH to handle cases
where DMA channel count is ≤ 32. The previous implementation used
integer division by 32, returning 0 for counts < 32, which caused
issues in dma_mcux_edma_multi_channels_irq_handler().
New logic:
- Return 1 for ≤ 32 channels (one uint32_t mask)
- Return dma_channels / 32 for > 32 channels
Ensures proper mask width calculation for all supported channel
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Add additional business check to waiting SUSPF to be set so
that the loop cannot be executed forever when the dma stream
is idle.
When the stream is not busy, then there is nothing to suspend.
However, if suspend was attempted for an idle stream, then the
changed loop waited forever SUSPF to be set. This could have
happened at least when serial api tx_abort() is called with
stm32u5 and tx dma transfer becoming ready about the same time
the tx_abort() API is called.
Fixes#103042
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
As per Zephyr coding guideline #59, "operands shall not be of an
inappropriate essential type". This makes sure boolean variables are
assigned true/false values, not 1/0.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
