Implement RTC support in counter driver for STM32WBA devices.
Changes are made according to the following specificities:
- Similarly to STM32U5, it is not connected to EXTI.
- On this series, there is no bit in BCDR register to enable RTC. Enabling
RTC is done directly via the RCC APB register bit
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
1. Issue a reset during init to ensure the registers
are in their reset state.
2. The value in counter_set_top_value was not written
to the register. This function now returns -ENOTSUP
3. Make sure the RTC is enabled before we issue RTC_Start
command.
4. Replace calls to SDK API's RTC_StartTimer and
RTC_StopTimer with RTC_EnableTimer
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Move the syscall_handler.h header, used internally only to a dedicated
internal folder that should not be used outside of Zephyr.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The counter_native_posix driver currently does not support top value
configuration, i.e. `ctr_set_top_value` returns `-ENOTSUP`. This commit
adds support for top value configuration, and with the counter API now
fully implemented, adds `counter` to `supported` peripherals for
native_posix target.
It also resolves an existing bug in which the
counter ISR did not reset upon reaching `TOP_VALUE`.
And adds support for multiple channels
Signed-off-by: Jason Wright <jason@jpw.nyc>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Split the read function into 2 versions (date and no date) since they
don't have common code.
It improves readability.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add support for using the sub second registers. It allows reading and
setting alarm with the sub second tick resolution.
The RTC module is configured to get as high frequency as possible, which
equals the source clock (RTCCLK) divided by 2. To get such frequency,
the asynchronous prescaler is set to 1.
According to RM, setting the asynchronous prescaler to a high value
minimize consumption, so the change increase the power consumption.
Use a config to enable the sub second support.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
RTC drivers uses only seconds, so transition to microseconds is
necessary.
Change way of calculation tick<->time to avoid unnecessary
conversations.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Synchronize reading two separate registers. In some edge cases the read
registers could point different dates.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The config values have been hardcoded as magic values. Introduce
universal calculation based on the DTS entries.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The PIT maximum load value may not be always 32-bit. Allow the SoC to
define this value from devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Depending on the SoC design, the PIT channel interrupts can be
individual or OR'ed together to a single interrupt line.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This periodic timer (PIT) has a single load value register for each
channel, which is currently used for both alarm and top callback APIs.
If using both APIs together (which is a valid use-case) it will write
to the same register causing unexpected behavior of the timer.
The nature of the PIT is to trigger an event (like interrupts) at a
certain rate, and not to produce single-shot events. Hence keep only top
callback functionality.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When timer calibration for SmartBond(tm) was added, opaque type
clock_control_subsystem_t that used to have device tree ordinal
number was changed to enum to allow values that are not in device
tree (like no clock selection).
During this process counter driver for SmartBond(tm) was not updated
accordingly, resulting in wrong frequency being reported to counter
driver.
Failure could be seen when samples/drivers/counter/alarm was execute on
da1469x_dk_pro board.
With this fix counter driver uses correct type when
clock_control_get_rate is called and counter test works again.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
The DT_INST_CLOCKS_CELL macro takes as the first argument the device
instance and not the cell index. This change correctly gets the second
index of the first device as intended.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
TC "test_single_shot_alarm_notop" is failing because there were 2 ISR
callbacks instead of one. this is because of invoking
ifx_cat1_counter_set_int_pending incorrectly. Updated
ifx_cat1_counter_set_alarm to fix this
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
SiLabs' sleeptimer driver supports several hardware peripherals, of
which the counter driver so far only supports the RTCC-based variant.
This patch adds support for the SYSRTC-based sleeptimer implementation,
which is required for Gecko SoCs that do not have an RTCC module.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
A recent factorisation moved F2 to non const TIM_TypeDef.
This is an error, move it back to const TIM_TypeDef.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
New RTC API seems to conflict with old RTC implementations based on
COUNTER
This scheme follows Zephyrproject-rtos issue 56599 while keeping backward
compatibility.
Signed-off-by: Kim Bøndergaard <kim.bondergaard@prevas.dk>
Since clocks aren't declared in the devicetree for the stm32mp1
co-processor. Read the resulting clock divider here instead.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
New nrfx release brings renamed macros and symbols in nrf_rtc.
This commit alligns RTC counter SHIM to it.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Added RTC driver that supports Motorola MC146818B
Enabled RTC set/get time and alarm, alarm callback
and update callback.
Counter and RTC uses same hardware in case of
Motorola MC146818, so they can't be used at a time.
Updated stand-alone mc146818 counter dts instances
to support rtc and counter with same compatible
string of "motorola,mc146818" on ia32, atom,
apollo_lake, elhart_lake and raptor_lake platforms.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Adapt the stm32 counter-timer driver to the stm32_ll function
prototype. Some stm32 families have
LL_TIM_OC_GetCompareCHx(TIM_TypeDef some others have
LL_TIM_OC_GetCompareCHx(const TIM_TypeDef.
This will fix compilation warning.
Adds the macro for stm32L0 16bit timers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add the stm32h5 serie to the stm32 RTC counter driver
EXTI Line is 17 (for stm32h50x or non-secure stm32h56x/h57x).
The drivers must Enable access to the BackUp Domain.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
