Updates the Infineon Counter and PWM drivers based on the TCPWM device
to connect with a clock. This update allows multiple devices to connect
to the same peripheral clock, and supports the TCPWM architecture of the
PSC3 device family.
Corrects initialization of the PWM on the PSC3 family to select the
correct output type.
Signed-off-by: John Batch <john.batch@infineon.com>
Add explicit clock configuration and enable calls during driver
initialization. The driver now attempts to configure the clock
subsystem before enabling it.
Note: -ENOSYS is temporarily ignored as not all clock control
drivers currently implement the configure API. This handling
should be removed once all clock drivers support configure.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Extend RTC driver to handle STM32U3 series specifics:
- Include STM32U3X in condition where RTC Alarm event is not routed to EXTI
- Use LL_RCC_RTC_ClockEnable call for STM32U3 instead of LL_RCC_EnableRTC
- Adapt counter_stm32_rtc driver for STM32U3 clock and EXTI handling
Signed-off-by: Antoine Pradoux <antoine.pradoux@st.com>
For devices like MCXE247, the FTM peripheral instance
has multiple interrupts. In this patch, add FTM_CONFIG_FUNC
macro to support single or multiple interrupts based on irq
number.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add implementation of the Infineon PSoC4 TCPWM-based counter driver.
- Provides basic counter operations
including start, stop, read, and set alarm.
- Supports configuration and initialization through Device Tree.
- Enables alarm callback handling for
precise time-based event generation.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Add a "run-mode" devicetree property to the NXP i.MX GPT counter
driver to control counter behavior on compare events.
The property supports two modes:
- "restart": Counter resets to 0 when reaching Compare Channel 1 value
- "free-run": Counter continues counting without reset
This change makes the GPT run mode configurable per device instance
instead of being hardcoded. The driver now derives the enableFreeRun
setting from devicetree, defaulting to "restart" mode.
This update aligns the GPT driver configuration approach with the
NXP LPTMR counter driver, which also uses devicetree properties
for runtime behavior configuration.
This provides consistency across NXP counter drivers in how hardware
behavior is controlled through devicetree.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Allow alarm_cfg->ticks to be 0 for immediate callback execution.
When ticks equals 0, set the interrupt pending instead of returning
-EINVAL, causing the ISR to fire immediately.
Implementation:
- Add irq_set_pending()/irq_is_pending() helpers for NVIC and GIC
- Store IRQ number in device config for pending operations
- Refactor timer state handling to eliminate duplication
- Update get_pending_int() to check both HW flags and NVIC/GIC state
This supports idle timer use cases where sleep duration may be zero
and eliminates the need for special-case handling in application code.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add device tree property to configure LPTMR free-running mode instead
of hardcoding it to disabled.
The freerunning property controls counter reset behavior:
- If false (default): Counter resets after compare match
- If true: Counter resets only on overflow, continues after compare
This allows per-instance configuration of the LPTMR timer mode based
on application requirements without code changes.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Added a counter driver for the RPI Pico/RP2040 that implements
programmable interval timer (PIT) functionality using the PWM HAL.
Signed-off-by: Jan Behrens <jan.behrens@navimatix.de>
Fix incorrect LPTMR prescaler/glitch filter mapping that led to wrong
frequency calculation and wrong hardware configuration.
- Calculate effective counter frequency correctly:
* Time Counter mode: divide by 2^(value + 1)
* Pulse Counter mode: divide by 2^value
- Map prescale-glitch-filter directly to the HAL enum (no offset math)
- Add prescale-glitch-filter-bypass DT boolean (default false)
- Restrict prescale-glitch-filter to 0..15 and update bindings/DTS users
- Add build-time validation for Pulse mode (value 0 requires bypass)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Refactor the Infineon TCPWM counter driver to use the TCPWM block base
address instead of the counter instance base address. This change aligns
with the standard Infineon PDL API which requires the TCPWM block base
and counter index as separate parameters.
This modification maintains functional compatibility while providing
better alignment with the underlying hardware abstraction layer.
This also aligns with PR feedback to move the ifx_tcpwm.h header file
from the include folder (public APIs) to the drivers folder. Instead,
this refactoring prepares to remove that header file entirely.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
According to the reference manual, 'When the BYPSHAD control bit is set
in the RTC_CR register [...] the value of one of the registers may be
incorrect if an RTCCLK edge occurs during the read operation'. We need
to read te subseconds register until two successive reads are equal.
Signed-off-by: Adrien Lessard <adrien.lessard.42@gmail.com>
- Update the driver to support the PSE84 device
- Update to new peripheral clock allocation scheme
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Drop cat1 from the binding files to enable reuse by other
category devices as well.
Fixes#99174
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Most of Espressif drivers ISRs are already running in IRAM area, except
those in this PR. Move ISRs accordingly so we avoid any
interrupt miss when cache is disabled.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Call pm_policy_device_power_lock_put/pm_policy_device_power_lock_get
to coordinate with system level power modes.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
The counter alarm irq shall set the match value
to the max top value after stopping the timer, otherwise
the next start of the lptmr counter may shortly match the
the previous match value thus cause test_valid_function_without_alarm
run failed.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Originally, function 'mcux_lptmr_get_pending_int' checks if both
TCF and TIE flags are set to determine if an interrupt is pending.
But function 'LPTMR_GetStatusFlags' only returns the status flags,
that is we will never get TIE flag from it. then the function
always returns false.
The correct approach is to read the CSR register directly and check
if both TIE and TCF bits are 1. If yes, there's a pending interrupt;
if not, there isn't.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The `ll` part of drivers' file name indicates that the implementation uses
the STM32Cube Low Level ("LL") library, which is not interesting because
there is only *one* STM32 driver implementation anyways (per IP variant).
Addtionnally, the presence of `ll` among STM32 drivers is not consistent.
Get rid of it for drivers of this class to match most other STM32 drivers.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
LPTMR is a commonly used wake-up source for many NXP MCUs and
may be used as the companion low-power timer for the Cortex-M
systick. This commit enabled LPTMR set and cancel ALARM functions.
Enabling single-shot alarm support requires reprogramming
the hardware compare register (COMPARE/CMR), which is the same
resource used for the periodic TOP callback. Because of this
hardware limitation, we added Kconfig 'CONFIG_COUNTER_MCUX_LPTMR_ALARM'
to select whether alarm support is enabled. When alarm support is
enabled the driver will not allow support set TOP operation at runtime
(attempts to set TOP will return -ENOTSUP); When alarm support is
disabled the driver will not allow set and cancel ALARM operation
at runtime (attempts to set and cancel ALARM will return -ENOTSUP).
Choose the configuration that matches your application's requirements.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Expose timer functionality from rv-3032-c7 via counter api.
I2C communication and IRQs are arbitrated via MFD parent driver
for rtc, sensor and counter at once.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Counter driver was not functional with STM32 advanced timers (like
TIMER1/8) due to them having more than one interrupt line.
This commit defines the proper interrupts for the advanced timers so that
they can be used as counters.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
New nrfx release contains major rework of nrfx drivers
instantiation making it easier to integrate with dts nodes.
Now, nrfx driver instances can no longer be `const`
because they contain driver runtime state.
Additionally, all nrfx drivers return `errno` error codes
instead of deprecated `nrfx_err_t`.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
For devices like MCXE247, the LPIT instance hase multiple
interrupts, however the current driver code just support
one interrupt. This patch has improved the code for this
requirement.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
This driver was renamed in
ab7a6de5bb
while the old kconfig options and dts binding were deprecated for 4.2
Let's remove them now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit enables configuration and integration of LCT counter by
including relevant source and kconfig files.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
For all STM32 drivers and SoC, replace the WRITE_REG macro and the
LL_xxx_WriteReg functions (defined in the STM32 HAL) by
stm32_reg_write defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
1.Include barrier.h to fix barrier_dsync_fence_full() not found issue
2.Support multiple channels for alarm function
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Clocks are requested automatically by hardware on the nRF54H.
Remove additional handling from device drivers, and disable
the now unmanaged clocks in the devicetree.
Updates:
- can_nrf
- counter_nrfx_timer
- uart_nrfx_uarte
- spi_nrfx_spim
- spi_nrfx_spis
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Use the `silabs,sleeptimer` chosen node instead of a devicetree
compatible to select the devicetree node for the counter.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Kconfig symbols for selecting HAL content should be part of the
HAL module integration, not defined in the SoC tree. Define the
sleeptimer symbol for WiSeConnect and SiSDK since both use it.
In the future, WiSeConnect should include the SiSDK configuration
and reuse it instead of redefining everything itself. This is a
larger scale refactor that this commit doesn't start tackling.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The existing formula assumed prescaler enumerations were consecutive,
which led to incorrect values being passed to HAL functions. Update
the code to calculate correct prescaler enumerations.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
In case RTC is used for system timer, it should not be used
as counter device. Dependency restricts counter driver to work
only with SYSTIM.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
In current code, if timer-mode-sel is 0(Timer Counter Mode),
bypass_prescaler_glitch will be 1, that makes prescaler setting
be bypassed. But this setting is very useful, especially for
long timing count.
In this patch, we update prescale-glitch-filter default value to 0,
to indicate prescaler and glitch filter are disabled, which comply
the existing devices DTS setting (prescaler = 1).
And if user sets prescale-glitch-filter properity other than 0,
we should set bypass_prescaler_glitch to false to make prescaler work,
and the clock frequence should be calculated with prescaler setting.
Update prescaler field in dt-bindings to tell developer should use
prescale-glitch-filter instead.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Disable RTC interrupts when cancelling alarm, and clear callback
data, to make sure no ISR/callback is serviced after alarm is
cancelled. Also, check programmed ticks in ISR to make sure
alarm triggered is not an outdated/cancelled event.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
