Implement the counter_api reset callback for the NXP LPC CTimer
driver to zero the timer counter register
while keeping the timer running.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Instead of hardcoded EXTI line numbers and raw LL API calls, align the
STM32 RTC Counter driver with its Real-Time Clock counterpart:
- obtain EXTI line number from Devicetree
- use the EXTI INTC API instead of raw LL API calls
Fixes the build issue observed on STM32N6.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
This introduces APIs for input capture on the STM32.
Rename callback in data to alarm_cb to prevent confusion with other
callbacks.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This introduces APIs for input capture.
A use case for this would be time stamping a rising and/or falling edge
where precision and lack of jitter is important. The only way to currently
do this in zephyr is to set up a GPIO interrupt and then read the counter
or kernel time... but this can have limitations of software such as the
processor may have a lot going on and can be subject to interrupt
latencies. Having a hardware 'latch' done of the rising and/or falling
edge with respect to a timer can eliminate these imprecisions.
How this is to be used, is that an application is to call
`capture_callback_set` with the configuration of the channel number, flags
(such as falling, rising, or both edges), and then a callback function.
Then the `capture_enable` function is to be called to enable this. The
callback has the timestamp of the edge in ticks and the edge that it
captured (rising or falling).
This also adds a 64 bit tick version for the capture callback.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This commit dsiables alarm counter before executing callback
function. Additionally, the alarm counter (external timer 7)
ticks are limited to 3 bytes. Return errno if the configured
value exceeds this range.
Tested with: samples/drivers/counter/alarm
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add counter RTC driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Basic counter operations
- Alarm configuration and callbacks
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within:
- `drivers/clock_control`
- `drivers/counter`
- `drivers/crypto`
- `drivers/dai`
- `drivers/debug`
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The counter_api_get_pending_int typedef returns uint32_t, but the
public counter_get_pending_int API, its inline implementation, and
its syscall handler all return int. Several drivers return raw hardware
register bitmasks that can have upper bits set; the implicit cast to
int would make those values appear negative, which callers could
misinterpret as error codes.
Change the public API, inline impl, and syscall handler to return
uint32_t to match the driver API typedef.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add ESP32-C5 support to the RTC counter driver. The C5 uses a
different LP timer interrupt status register field
(soc_wakeup_int_st) compared to other SoCs (alarm), requiring a
SoC-specific macro for the interrupt status check.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds runtime device power management support to MAX32 Wake-up Timer
driver. The suspend routine is intentionally left unimplemented to
allow the Wake-up Timer to continue counting while the device is in
sleep mode.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Fix two bugs in the timer counter driver that prevent tests
from passing.
-EBUSY should be returned from set_top_value() if there are
active alarms, not if the counter has been started.
The ISR should only process interrupts that are currently enabled,
not all pending flags.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added Silabs Kconfig support for counter driver and implemented the
counter APIs using protimer underneath.
Signed-off-by: sree sreerajatha <sree.sreerajatha@silabs.com>
When all LPTMR instances are reserved as the system
timer, the counter driver has no instances to create.
The static init and ISR functions become unused,
causing -Werror=unused-function build failures.
Guard the entire driver body with a preprocessor check
that counts usable (non-system-timer) LPTMR instances.
When the count is zero the file compiles to nothing.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add counter timer driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver is based on the hardware timer and supports:
- Relative alarm configuration
- Top value configuration
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Replace the single-instance assumption with a zephyr,system-timer chosen
node approach. The timer driver reads its hardware instance directly from
DT_CHOSEN(zephyr_system_timer) instead of assuming instance 0. The
counter driver skips whichever instance is designated as the system timer,
allowing both drivers to coexist on SoCs with multiple LPTMR instances.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
counter_handlers.c was missing verifier/marshaling coverage for multiple
counter APIs, especially 64-bit helpers.
This change adds the missing z_vrfy handlers and corresponding mrsh
includes so the syscall layer matches the public counter API surface.
Missing functions now covered in drivers/counter/counter_handlers.c:
z_vrfy_counter_get_frequency_64
z_vrfy_counter_us_to_ticks_64
z_vrfy_counter_ticks_to_us_64
z_vrfy_counter_ns_to_ticks
z_vrfy_counter_ns_to_ticks_64
z_vrfy_counter_ticks_to_ns
z_vrfy_counter_ticks_to_ns_64
z_vrfy_counter_reset
z_vrfy_counter_set_value
z_vrfy_counter_set_value_64
z_vrfy_counter_get_max_top_value_64
z_vrfy_counter_set_top_value_64
z_vrfy_counter_set_channel_alarm_64
z_vrfy_counter_get_top_value_64
z_vrfy_counter_get_guard_period_64
z_vrfy_counter_set_guard_period_64
z_vrfy_counter_get_pending_int was removed from the macro as it
returns a uint32_t and not exactly an int.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixes the counter running after initialization and the counter running
after calling counter_set_top_value, regardless of previous state.
Also adjusts the tests.
Signed-off-by: Jan Behrens <jan.behrens@navimatix.de>
Replace busy-wait synchronization delay with a safety window mechanism
to prevent missed alarm compares when set too close to current counter
value.
- Remove k_busy_wait(100U) after setting API compare value
- Use MINIMUM_RTCVAL/MINIMUM_APIVAL as safety window thresholds
- Trigger SW-pending interrupts for alarms within safety window
- Fix absolute alarm late-to-set detection using forward distance
- Reduce counter test iterations from 100 to 1
This ensures reliable alarm delivery without blocking delays.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add Counter driver support for Renesas RZ/A2M
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
On MAX32 SoCs, some timer instances can use an external clock input.
This commit ensures that when the external clock is selected as the
source, its frequency is read and used correctly.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
MAX32 timers can optionally use external input/output pins.
Enable pinctrl support in the counter driver so these pins
can be properly configured via device tree.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Reduce the complexity of the set-alarm and set-top functions.
Improve the error handling.
Replace IRQ macros with static inline functions to centralize GIC/NVIC
conditional handling.
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add counter driver for timer on Silicon Labs series 2.
Tested by building and running the sample on realboard
slwrb4180b and xg24_rb4187c.
Signed-off-by: Phuc Hoang <donp172748@gmail.com>
Allow the ADI MAX32 platform use `counter_reset` and `counter_set_value`
- `reset` clears the counter
- `set_value` sets it to a given value
Signed-off-by: James Roy <rruuaanng@outlook.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Select COUNTER_64BITS_TICKS for ACE counters to enable this
functionality by default.
This restores the default state which was disabled by recent commits.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Wrap counter_ace_v1x_rtc_get_value in #ifdef
to avoid an unused function warning when
64-bit ticks are disabled.
Fixes 7fc848153c
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
As per Zephyr coding guideline #59, "operands shall not be of an
inappropriate essential type". This makes sure boolean variables are
assigned true/false values, not 1/0.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Drop `counter_stm32_reset_timer`, introduced in PR #94189 (01a00d5),
as it duplicates the existing `counter_stm32_reset` functionality.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add explicit clock configuration and enable calls during driver
initialization.
Note: -ENOSYS is temporarily ignored as not all clock control
drivers currently implement the configure API. This handling
should be removed once all clock drivers support configure.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Fix incorrect diff calculation for relative alarms that caused alarm
callbacks to never fire. The original code calculated diff as
(alarm_cfg->ticks - now), which caused unsigned underflow when
now > alarm_cfg->ticks, resulting in a huge diff value that
incorrectly triggered the late alarm path and set callback to NULL.
For relative alarms, the diff should simply be the ticks value since
it already represents the delay from the current time.
Also add channel validation to return -ENOTSUP for chan_id > 0 since
ESP32 timer hardware only supports one alarm comparator per timer.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
As per Zephyr coding guideline #59, "operands shall not be of an
inappropriate essential type". This makes sure boolean variables are
initialized with true/false, not 1/0.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add a kconfig to be used as a flag for indicating if it supports 64b
ticks and another flag which will enable the 64b api. The kconfig
indicating that it supports 64b is a dependency of the kconfig that
will enable the api.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Some counters, such as those that use fractional adders, tick at
resolutions greater than 4294967295Hz. This changes the freq in the common
info to a uint64_t. This adds a KConfig that can be selected by a driver.
This also has the counter ticks to sec (and vice versa) helper functions
call the get frequency for 64 bits if the kconfig is selected.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
