counter: stm32 rtc: handle sub second registers
Add support for using the sub second registers. It allows reading and setting alarm with the sub second tick resolution. The RTC module is configured to get as high frequency as possible, which equals the source clock (RTCCLK) divided by 2. To get such frequency, the asynchronous prescaler is set to 1. According to RM, setting the asynchronous prescaler to a high value minimize consumption, so the change increase the power consumption. Use a config to enable the sub second support. Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
This commit is contained in:
Dawid Niedzwiecki
Carles Cufí
parent
322f7980c5
commit
49f9aa7d12
3 changed files with 137 additions and 10 deletions
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@ -44,4 +44,13 @@ config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS
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help
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Keep the counter value after each reset.
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config COUNTER_RTC_STM32_SUBSECONDS
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bool "Use the subseconds as a basic tick."
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depends on !SOC_SERIES_STM32F1X
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help
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Use the subseconds as the basic time tick. It increases resolution
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of the counter. The frequency of the time is RTC Source Clock divided
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by 2. It is the clock after the first asynchronous prescaler.
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The config increases power consumption.
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endif # COUNTER_RTC_STM32
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@ -70,7 +70,12 @@ LOG_MODULE_REGISTER(counter_rtc_stm32, CONFIG_COUNTER_LOG_LEVEL);
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#endif /* DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSI */
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#if !defined(CONFIG_SOC_SERIES_STM32F1X)
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#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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#define RTC_ASYNCPRE BIT_MASK(7)
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#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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/* Get the highest possible clock for the subsecond register */
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#define RTC_ASYNCPRE 1
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else /* CONFIG_SOC_SERIES_STM32F1X */
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#define RTC_ASYNCPRE (RTCCLK_FREQ - 1)
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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@ -78,6 +83,12 @@ LOG_MODULE_REGISTER(counter_rtc_stm32, CONFIG_COUNTER_LOG_LEVEL);
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/* Adjust the second sync prescaler to get 1Hz on ck_spre */
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#define RTC_SYNCPRE ((RTCCLK_FREQ / (1 + RTC_ASYNCPRE)) - 1)
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#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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typedef uint32_t tick_t;
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#else
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typedef uint64_t tick_t;
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#endif
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struct rtc_stm32_config {
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struct counter_config_info counter_info;
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LL_RTC_InitTypeDef ll_rtc_config;
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@ -88,6 +99,9 @@ struct rtc_stm32_data {
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counter_alarm_callback_t callback;
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uint32_t ticks;
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void *user_data;
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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bool irq_on_late;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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};
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static inline ErrorStatus ll_func_init_alarm(RTC_TypeDef *rtc, uint32_t format,
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@ -136,6 +150,17 @@ static inline void ll_func_disable_interrupt_alarm(RTC_TypeDef *rtc)
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#endif
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}
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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static inline uint32_t ll_func_isenabled_interrupt_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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return LL_RTC_IsEnabledIT_ALR(rtc);
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#else
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return LL_RTC_IsEnabledIT_ALRA(rtc);
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#endif
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}
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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static inline void ll_func_enable_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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@ -180,13 +205,16 @@ static int rtc_stm32_stop(const struct device *dev)
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return 0;
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}
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static uint32_t rtc_stm32_read(const struct device *dev)
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tick_t rtc_stm32_read(const struct device *dev)
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{
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#if !defined(COUNTER_NO_DATE)
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struct tm now = { 0 };
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time_t ts;
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uint32_t rtc_date, rtc_time, ticks;
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uint32_t rtc_date, rtc_time;
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tick_t ticks;
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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uint32_t rtc_subseconds;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else
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uint32_t rtc_time, ticks;
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#endif
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@ -198,7 +226,15 @@ static uint32_t rtc_stm32_read(const struct device *dev)
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#if !defined(COUNTER_NO_DATE)
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do {
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rtc_date = LL_RTC_DATE_Get(RTC);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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do {
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rtc_time = LL_RTC_TIME_Get(RTC);
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rtc_subseconds = LL_RTC_TIME_GetSubSecond(RTC);
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} while (rtc_time != LL_RTC_TIME_Get(RTC));
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#else /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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rtc_time = LL_RTC_TIME_Get(RTC);
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#endif
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} while (rtc_date != LL_RTC_DATE_Get(RTC));
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#else
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@ -225,7 +261,16 @@ static uint32_t rtc_stm32_read(const struct device *dev)
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ts -= T_TIME_OFFSET;
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__ASSERT(sizeof(time_t) == 8, "unexpected time_t definition");
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ticks = ts * counter_get_frequency(dev);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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/* The RTC counts up, except for the subsecond register which counts
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* down starting from the sync prescaler value. Add already counted
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* ticks.
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*/
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ticks += RTC_SYNCPRE - rtc_subseconds;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else
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ticks = rtc_time;
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#endif
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@ -234,25 +279,43 @@ static uint32_t rtc_stm32_read(const struct device *dev)
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}
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static int rtc_stm32_get_value(const struct device *dev, uint32_t *ticks)
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{
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*ticks = (uint32_t)rtc_stm32_read(dev);
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return 0;
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}
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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static int rtc_stm32_get_value_64(const struct device *dev, uint64_t *ticks)
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{
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*ticks = rtc_stm32_read(dev);
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return 0;
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}
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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static void rtc_stm32_set_int_pending(void)
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{
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NVIC_SetPendingIRQ(DT_INST_IRQN(0));
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}
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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#if !defined(COUNTER_NO_DATE)
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struct tm alarm_tm;
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time_t alarm_val;
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time_t alarm_val_s;
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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uint32_t alarm_val_ss;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else
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uint32_t remain;
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#endif
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LL_RTC_AlarmTypeDef rtc_alarm;
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struct rtc_stm32_data *data = dev->data;
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uint32_t now = rtc_stm32_read(dev);
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uint32_t ticks = alarm_cfg->ticks;
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tick_t now = rtc_stm32_read(dev);
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tick_t ticks = alarm_cfg->ticks;
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if (data->callback != NULL) {
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LOG_DBG("Alarm busy\n");
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@ -271,10 +334,14 @@ static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id,
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* that tick+1 event occurs before alarm setting is finished.
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*/
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ticks += now + 1;
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alarm_val = (time_t)(ticks / counter_get_frequency(dev)) + T_TIME_OFFSET;
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alarm_val_s = (time_t)(ticks / counter_get_frequency(dev)) + T_TIME_OFFSET;
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} else {
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alarm_val = (time_t)(ticks / counter_get_frequency(dev));
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alarm_val_s = (time_t)(ticks / counter_get_frequency(dev));
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}
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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alarm_val_ss = ticks % counter_get_frequency(dev);
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else
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if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
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remain = ticks + now + 1;
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@ -289,9 +356,13 @@ static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id,
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#endif
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#if !defined(COUNTER_NO_DATE)
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#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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LOG_DBG("Set Alarm: %d\n", ticks);
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#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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LOG_DBG("Set Alarm: %llu\n", ticks);
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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gmtime_r(&alarm_val, &alarm_tm);
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gmtime_r(&alarm_val_s, &alarm_tm);
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/* Apply ALARM_A */
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rtc_alarm.AlarmTime.TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
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@ -319,11 +390,34 @@ static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id,
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}
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LL_RTC_DisableWriteProtection(RTC);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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/* Care about all bits of the subsecond register */
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LL_RTC_ALMA_SetSubSecondMask(RTC, 0xF);
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LL_RTC_ALMA_SetSubSecond(RTC, RTC_SYNCPRE - alarm_val_ss);
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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ll_func_enable_alarm(RTC);
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ll_func_clear_alarm_flag(RTC);
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ll_func_enable_interrupt_alarm(RTC);
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LL_RTC_EnableWriteProtection(RTC);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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/* The reference manual says:
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* "Each change of the RTC_CR register is taken into account after
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* 1 to 2 RTCCLK clock cycles due to clock synchronization."
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* It means we need at least two cycles after programming the CR
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* register. It is confirmed experimentally.
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*
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* It should happen only if one tick alarm is requested and a tick
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* occurs while processing the function. Trigger the irq manually in
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* this case.
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*/
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now = rtc_stm32_read(dev);
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if ((ticks - now < 2) || (now > ticks)) {
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data->irq_on_late = 1;
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rtc_stm32_set_int_pending();
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}
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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return 0;
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}
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@ -380,13 +474,20 @@ void rtc_stm32_isr(const struct device *dev)
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uint32_t now = rtc_stm32_read(dev);
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if (ll_func_is_active_alarm(RTC) != 0) {
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if (ll_func_is_active_alarm(RTC) != 0
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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|| (data->irq_on_late && ll_func_isenabled_interrupt_alarm(RTC))
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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) {
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LL_RTC_DisableWriteProtection(RTC);
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ll_func_clear_alarm_flag(RTC);
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ll_func_disable_interrupt_alarm(RTC);
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ll_func_disable_alarm(RTC);
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LL_RTC_EnableWriteProtection(RTC);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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data->irq_on_late = 0;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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if (alarm_callback != NULL) {
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data->callback = NULL;
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@ -500,7 +601,12 @@ static const struct stm32_pclken rtc_clk[] = STM32_DT_INST_CLOCKS(0);
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static const struct rtc_stm32_config rtc_config = {
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.counter_info = {
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.max_top_value = UINT32_MAX,
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#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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/* freq = 1Hz for not subsec based driver */
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.freq = RTCCLK_FREQ / ((RTC_ASYNCPRE + 1) * (RTC_SYNCPRE + 1)),
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#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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.freq = RTCCLK_FREQ / (RTC_ASYNCPRE + 1),
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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.flags = COUNTER_CONFIG_INFO_COUNT_UP,
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.channels = 1,
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},
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@ -521,6 +627,9 @@ static const struct counter_driver_api rtc_stm32_driver_api = {
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.start = rtc_stm32_start,
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.stop = rtc_stm32_stop,
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.get_value = rtc_stm32_get_value,
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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.get_value_64 = rtc_stm32_get_value_64,
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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.set_alarm = rtc_stm32_set_alarm,
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.cancel_alarm = rtc_stm32_cancel_alarm,
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.set_top_value = rtc_stm32_set_top_value,
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@ -18,3 +18,12 @@ tests:
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- CONFIG_ZERO_LATENCY_IRQS=y
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extra_args:
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DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;boards/nrf52840dk_nrf52840_zli.overlay"
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drivers.counter.basic_api.stm32_subsec:
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tags:
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- drivers
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- counter
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depends_on: counter
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platform_allow: nucleo_f429zi
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timeout: 600
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extra_configs:
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- CONFIG_COUNTER_RTC_STM32_SUBSECONDS=y
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