Fix alarm setting when timer has overflown beyond 32-bit boundary.
Timer is 48-bit, so it requires high word to be programmed along
the 32-bit word managed by the driver.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Usage of stm32xxxx_ll_tim.c has been removed so we can also remove the
selection of USE_STM32_LL_TIM from the Kconfig.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove the calls to LL_RTC_Init, LL_RTC_DeInit and LL_RTC_ALMA_Init in
the RTC counter driver. This avoids calling functions from
stm32xxxx_ll_rtc.c.
They are replaced by a set of simpler functions from the header file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This header file isn't required, and prevents the driver building for
the RISC-V based Hazard3 cores.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
- Add a new counter driver implementation based on the PDL for
Infineon CAT1B devices. This enables support for hardware
counters on the PSC3M5 platform.
- Add IFX_TCPWM_Counter_DeInit and IFX_TCPWM_Counter_Init
macros to include/zephyr/drivers/timer/ifx_tcpwm.h
and sort all of the macros in that file
Signed-off-by: Yurii Lozynskyi <yurii.lozynskyi@infineon.com>
Switch to using the new NXP_ENABLE_WAKEUP_SIGNAL and
NXP_DISABLE_WAKEUP_SIGNAL macros to avoid adding
platform specific calls in the Zephyr drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Remove the calls to LL_TIM_StructInit and LL_TIM_Init in the counter
driver. This avoids calling functions from stm32xxxx_ll_tim.c.
They are replaced by a set of simpler functions from the header file.
Also replaces some macros that used constants coming from the HAL. Use
an equivalent coming purely from the LL.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The parameter for LPIT_DisableInterrupts should be
lpit_interrupt_enable_t, not channel id.
Besides, improve the code to use BIT macro for shift
operation.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Disable the shadow registers bypass in init function before RTC
deinitialisation to avoid infinite loop as the bit cases the RSF bit
to be kept in 0. The systick is not working in PRE_KERNEL_1 so it will
never timeout.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
1.Update dts bindings to move clock-source properties from
nxp,ftm-pwm.yaml to nxp,ftm.yaml.
2.Provide counter driver based on FTM driver from NXP mcux-sdk-ng
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Cancelling the alarm needs to reset the callback to NULL, else setting
an alarm subsequently will never work.
chan_id parameter being unused, using ARG_UNUSED() relevantly then.
Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
Issue: the alarm 1 do not generate interrupt
There are three compare registers in a SAM TC channel:
RA --> alarm 0
RB --> alarm 1
RC --> top_value
By default the RB/TOIB was configured as an input and no longer
generates interrupt.
Set the direction of TIOB to output for alarm 1 interrupt.
Fixeszephyrproject-rtos/zephyr#85018
Signed-off-by: CHEN Xing <xing.chen@microchip.com>
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function counter_stm32_get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The SNVS RTC can act as a wakeup source, re-use pm.yaml properties and
remove the Kconfig symbol.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
1.Add dts bindings nxp,lpit-channel.yaml and nxp,lpit.yaml
2.Provide counter driver based on lpit driver from NXP mcux-sdk-ng
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Update handling of fast instances to take into account whether
CONFIG_CLOCK_CONTROL is enabled or not.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Currently, the STM32 TIM counter driver will always register itself as ISR
for interrupts[0] of the timer node. This works fine for timers which have
a single "global" interrupt but not for others (e.g., Advanced Timer) which
have separate IRQ lines for various events.
Borrow the pattern from PWM driver: use the "cc" interrupt if it exists on
timer node, otherwise use the "global" interrupt. If neither of those are
found, a build error is raised to ensure silent failures cannot occur.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Issue: the alarm 1 do not generate interrupt
There are three compare registers in a SAM TC channel:
RA --> alarm 0
RB --> alarm 1
RC --> top_value
By default the RB/TOIB was configured as an input and no longer
generates interrupt.
Set the direction of TIOB to output for alarm 1 interrupt.
Fixeszephyrproject-rtos/zephyr#85018
Signed-off-by: CHEN Xing <xing.chen@microchip.com>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Fix condition in which alarm stops working after a certain amount
of time. Hardware timer is 54-bit, yet it is treated as 32-bit by
the counter driver. To allow alarm event by hardware comparators,
counter high word must be loaded into the register along with
the lower word managed by the driver.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Previously, the CMSDK APB dual timer driver hardcoded the counter
clock frequency to 24 MHz, which limits reuse across SoCs and
boards with different timer clock sources.
This patch replaces the hardcoded frequency with a value derived
from the device tree's `clocks` phandle, using the
`clock-frequency` property of the referenced clock controller node.
If the property is missing, it falls back to a default 24 MHz.
Signed-off-by: Lidor T <lidor@exibit-iot.com>
Restructured counter and timer.
CTimer/Timer is now parent to pwm and counter.
Created PWM driver and tied to pwm and pwm-led
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Previously, the CMSDK APB timer driver hardcoded the
counter clock frequency to 24 MHz, which limits reuse
across SoCs and boards with different timer clock
sources.
This patch replaces the hardcoded frequency with a value
derived from the device tree's `clocks` phandle, using
the `clock-frequency` property of the referenced clock
controller node. If the property is missing, it falls
back to a default 24 MHz and issues a build-time
warning.
Signed-off-by: Lidor T <lidor@exibit-iot.com>
There was an unnecessary nested `if` in `ifx_cat1_counter_init` with the
same condition already checked in the outer block.
This results in dead and redundant code with no functional impact but
harms readability.
The inner `if (rslt != CY_RSLT_SUCCESS)` was removed to clean up the
function.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
The function counter_rz_gtm_set_alarm was accessing alarm_cfg->flags and
alarm_cfg->ticks before verifying that alarm_cfg is non-NULL.
This could lead to undefined behavior or crashes if a NULL pointer is
passed.
The pointer check has been moved before any dereference to fix this bug.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Add missing backup domain access requests in STM32 RTC counter
driver that are needed to modify RTC registers.
Remove backup domain access requests in rtc_stm32_read() since this
function only reads RTC registers and backup domain access protection
protects RTC registers against write accesses only.
Fixes issue 92511.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access. When we're done accessing RTC registers and
other protected resource, release the access refcount.
By the way, simplify rtc_stm32_read() when COUNTER_NO_DATE is defined
that used a useless extra local variable.
By the way, correct stm32_hsem.h header file inclusion that requires
brackets (<>) delimiters, not double quotes, as per convention header
location.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
CLOCK_CONTROL is required for fast instances of UART and COUNTER,
help select it when possible. The fast instances are UARTE120,
TIMER120 and TIMER121, and CLOCK_CONTROL is not supported for
CPUFLPR and CPUPPR even when the fast instances are used.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
1.correct timer register control flow
2.select timer interrupt rising edge trigger, instead of default
level trigger
Stress test: top timer fires interrupt every 300ms for 18 hours.
The result is that we don't lose any interrupts.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Currently there is a mismatch between the naming of the hardware and
the drivers targetting the hardware. nrf2_ is used instead of
the actual bindings names, like nrf2_audiopll instead of
nrfs_audiopll. This makes it hard to map drivers to the hardware
they are targetting.
There is historical reason for some of this, namely the same binding
name was used for different hardware, which is why nrf2_ was used
on newer platforms. This is no longer the case though, so drivers
and configs can be named according to the hardware without conflict.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Counting module, Capture block (measure input signal period/time) and
Compare block (to generate time expiry, output waveform like PWM).
Add a support for counter driver with alarm and counter top functions.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
User callback can be used to re-trigger the alarm.
In such case, copy current callback before it is overritten.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
