Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for PM policy device constraints to the MCUX LPADC driver.
This allows the driver to specify that certain power states should be
disabled when the device is active, which can help ensure proper operation
and reduce power consumption.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add shell commands for the ADC emulator driver (zephyr,adc-emul) to
allow runtime configuration of emulated ADC values during testing and
development.
The new shell commands support:
- Setting constant raw ADC codes for a channel
- Setting constant input voltage in millivolts for a channel
Commands are dynamically populated with available ADC emulator devices
from the devicetree. This enables interactive testing of ADC-dependent
code without requiring physical hardware or signal generators.
Example usage:
adc_emul <device> raw <channel> <value>
adc_emul <device> mv <channel> <millivolts>
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Change the ADC emulator driver to accept differential mode configuration
instead of rejecting it with -ENOTSUP. When differential mode is requested,
the driver now logs a warning that samples are provided as raw codes and
continues operation.
This allows testing of ADC configurations that use differential mode
without requiring the emulator to implement full differential conversion
logic. The raw code values can still be set via shell commands or API
calls for testing purposes.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add explicit clock configuration and enable calls during driver
initialization.
Note: -ENOSYS is temporarily ignored as not all clock control
drivers currently implement the configure API. This handling
should be removed once all clock drivers support configure.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Added support for the low side power switch pin used for switching
DUTs attached to the ADC. The switch is configured though the
drivers device tree.
Signed-off-by: Noah Stephens <nstephens78@gmail.com>
Add driver for the Infineon SAR ADC peripheral with device tree
binding. The driver uses a generic compatible (infineon,sar-adc)
with an infineon,version property to differentiate IP block
revisions (v2, v3). Features include:
- Single-ended and differential channel configuration
- Configurable resolution (8-12 bits)
- Multiple voltage reference sources (internal, VDDA, VDDA/2, external)
- Channel reference validation against block-level vref-src
- Hardware compensation for SAR v2/v3 single-ended channel limitation
- Interrupt-driven conversion completion
- Integration with peripheral clock control
The driver includes a compile-time per-instance API structure to
correctly report reference voltage to the ADC framework for accurate
raw-to-millivolts conversion.
Tested on CY8CKIT-041S-MAX (SAR v2) and CY8CPROTO-041TP (SAR v3) boards.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
the ads1119 has its own driver connected to CONFIG_ADC_ADS1119,
so remove it from CONFIG_ADC_ADS1X1X. Also the driver under
CONFIG_ADC_ADS1X1X doesn't support it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
When adc resolution is set to 12bit (lpadc provides 12bit or 16bit)
and the FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS is not enabled,
the function mcux_lpadc_isr saves the measured value to variable result
but this value is not used after that,
(unless the FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS is enabled).
This change fixed the issue.
Tested on FRDM-MCXA266 with adc_dt zephyr sample.
Signed-off-by: Martin Martincek <martin.martincek@nxp.com>
As per Zephyr coding guideline #59, "operands shall not be of an
inappropriate essential type". This makes sure boolean variables are
assigned true/false values, not 1/0.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Initial implementation of an adc driver for the ads79xx series of
spi-adc chips.
This driver sets the device in auto-1 mode, and supports devices
in the series, with different resolutions (12/10/8-bit),
and number of channels.
Signed-off-by: James Walmsley <james@fullfat-fs.co.uk>
Fix offset calibration handling and improve type safety in the
LPADC driver:
- Change offset_a and offset_b from uint32_t to int16_t to match HAL API.
- Add explicit int16_t casts when initializing offset values from DT.
- Add conditional logic to handle platforms with single offset trim.
- Use LPADC_SetOffsetValue() with appropriate parameters based on
FSL_FEATURE_LPADC_OFSTRIM_COUNT when auto-calibration is disabled.
This ensures proper offset calibration on all supported platforms and
prevents potential type mismatch issues.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Fix inconsistent formatting in the LPADC driver by:
- Consolidating multi-line preprocessor conditionals onto single lines
- Aligning macro continuation backslashes consistently
- Fixing indentation in structure initialization and macro definitions
- Removing unnecessary line breaks in function calls
No functional changes, formatting cleanup only.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Bind registers to the local variable in the ti_adc_init() function
after mapping the address space via DEVICE_MMIO_MAP.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Allow using other references by removing the hard requirement on it being
internal. To be able to use internal voltage, the DT property ti,vrefp can
be used, otherwise it is ignored.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
RSI_ADC_ClkDivfactor() is called from system clock_control. But in fact, it
controls the internal division factor of the ADC hardware block.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
ADC_CONTEXT_USES_KERNEL_TIMER is required for ADC_CONTEXT_INIT_TIMER().
However, it should be defined in the Zephry driver, not in the Wiseconnect
integration.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Handle the return value of am_hal_adc_power_control() during ADC
initialization.
The previous code overwrote the return value before it was checked,
which could silently ignore failures when powering on the ADC.
Fix this by validating the return code and propagating an error if
the operation fails.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Configure the reference buffers when using external reference voltage for a
channel. For the internal reference the datasheet[1] recommends that the
buffers are disabled and for external references they should be disabled if
REFPx/REFNx is close to AVDD/AVSS. After reset the positive reference
buffer is enabled and the negative is disabled. The default values
correspond to the example circuit for a two-wire and four-wire PT100 RTD
measurement with low-side reference.[2][3]
The values configured by the driver are maybe a little opinionated, but the
current behaviour is kept to avoid surprises for people that are happy with
the drivers defaults.
The change applies to both ads11xs0x and ads124xs0x series.
Link: [1]: https://www.ti.com/lit/ds/symlink/ads124s08.pdf
Link: [2]: https://www.ti.com/lit/an/sbaa329b/sbaa329b.pdf
Link: [3]: https://www.ti.com/lit/an/sbaa336b/sbaa336b.pdf
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Some NXP SAR ADC variants don't implement the MCR[ADCLKSEL] field.
Add conditional compilation guards to define compatibility macros
that evaluate to 0 when ADCLKSEL is not available, allowing the
driver to compile across different NXP SoCs.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
As reported in #101190, running adc_sequence sample on stm32f103c8 with 8
ADC channels causes all subsequent conversions after the first to be one
channel shifted. This is because writing to CR2 with ADON=1 and no other
changes triggers a conversion (which is why the bug happens on all
but the first sequence). Adding this check will ensure that CR2 is only
written when the DMA bit changes.
Signed-off-by: Benedek Kupper <kupper.benedek@gmail.com>
Add ADC driver support for Renesas RZ/A2M
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Some internal _CONCAT* macros were used throughout the file. Replace them
with the simple CONCAT macro.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Rework the way to set the STM32 ADC resolution.
Instead of using special macros in device tree, supported resolutions are
now simply listed as an array.
From this array, the driver defines two tables. The first contains the same
values as the array, the second contains the LL macros for each resolution.
When setting the resolution, the driver checks the value with the first
table, then sets it with the second table.
The two tables are defined for each enabled ADC instance so there are no
conflicts if different ADC have different resolutions.
For STM32H7, this changes the internal values used for 14 and 12-bit
resolutions, from 0b101/110 to 0b001/010 respectively, i.e. it uses the
so-called "legacy" resolutions instead of the "power-optimized" ones.
Note that AN5354 indicates: "The optimized modes have better power
consumption figures. The standard modes have better parameters, but
power consumption is not optimized and is comparable to 16-bit mode."
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Enabled async read function for NXP SAR ADC driver by implementing
nxp_sar_adc_read_async() and modifying nxp_sar_adc_read() to call it
with a NULL signal for synchronous operation.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
set_sequencer() never reports errors and always returns 0.
The error check at the call site is therefore dead code.
Make the function void and drop the unused error handling.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
When a driver requires the usage of a low level driver subsystem
(like SPI, I2C, DMA...), it shall enable it instead of depending on it.
Also, make DMA usage depend on its DT properties being defined.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add two new definitions, ADC_SAR_IP_HW_REG_SIZE and
ADC_SAR_IP_CHAN_2_BIT, to eliminate the inclusion of
Adc_Sar_Ip_HwAccess.h, since this header file does not
exist for the S32K5 platform.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit enhances the SAR ADC driver by adding
support for clock frequency selection. The clock
frequency can now be configured via the devicetree,
allowing for better optimization of ADC performance
based on application requirements.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add a Zephyr ADC driver for the Microchip G1 ADC peripheral
with support for differential mode, multi-channel sequencing,
oversampling, and NVM-based factory calibration.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Zephyr's current ADC API only supports 32 logical channels,
which is inadequate for SAR ADCs on certain SoCs. For instance,
the ADC on the MCXE31B has 64 hardware channels. The previous
implementation used a one-to-one mapping between logical and
hardware channels. In the new SAR ADC driver version, we bind
hardware channels to logical channels via the zephyr,input-positive
property, enabling us to access any channel.
Currently, only imx93 uses this ADC. To maintain the bisectability
of Zephyr commits, in this commit we will also modify the imx93-related
files, inlcuding:
1. Update the clock_control_mcux_ccm_rev2.c to use the new Kconfig
option 'CONFIG_ADC_NXP_SAR_ADC'.
2. Add properties to the imx93_evk_mimx9352_m33.overlay of the adc_api
testcase.
Now the sar adc is native driver, so, remove
CONFIG_MCUX_COMPONENT_driver.sar_adc from the glue cmake.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Drop cat1 from the binding files to enable reuse by other
category devices as well.
Fixes#99174
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
