Check that the channels are configured with the reference
ADC_REF_INTERNAL when compiling the driver.
Signed-off-by: Colin Evrard <colin.evrard@mind.be>
SHIM Nordic modification for the ADC driver controlling the SAADC
peripheral. Replaced HAL based implementation in favor of nrfx driver.
As a next step, it is planned to implement a feature that will allow
the peripheral SAADC timer to be used for sampling, and for this it is
necessary to use the nrfx driver in this SHIM.
This will allow more accurate and faster sampling than the kernel
mechanism currently provides.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Corrected the timeout condition in the ti_adc_sequencer_start function
to ensure proper timeout handling during ADC sequencer operations.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
For a long time (since version 3.3.0) nrfx contained an incorrectly
defined symbol NRF_SAADC_8BIT_SAMPLE_WIDTH that was set to 8 for nRF54L
and nRF54H Series SoCs, which was probably only true for very early
engineering revisions of those. Based on this, the adc_nrfx_saadc driver
was incorrectly writing consecutive 8-bit samples in supplied buffers,
cutting off the highest 8 bits of the results. And for sequences with
multiple channels, it was even causing that the results written as
16-bit words by hardware were partially overwritten in next iteration.
In nrfx 3.12.0 (see commit f46798fa55)
this was finally corrected - the symbol is now deprecated and it is
always set to 16. This commit is a follow-up to the above and removes
parts of adc_nrfx_saadc that now became dead code to prevent further
confusion regarding 8-bit sampling.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
It is not an error if the clock source is already enabled. This
may happen if a bootloader has used the peripheral and not
de-initialized it before booting the application.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Prevent integer underflow when sequence->channels is 0.
Add an explicit check before calling find_msb_set().
Coverity CID: 487765
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
The ADC has a dedicated interface for communicating with the DMA.
The ADC module provides four interrupt sources (one for each
conversion result storage register) which can be configured to
source the DMA trigger.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Add check for odr <= 0 and cast odr to uint32_t before multiplication
to avoid integer overflow and division by zero.
Fixes: CID 489220
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
This patch adds the ADC driver for TI K3 family of SoCs. Technical
reference can be found in the Technical Reference Manual (TRM) of the
board.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Add driver for the microchip MCP3561/2/4R ADC. Registers lock and
CRCCFG protection mecanism is not implemented. Tested on an MCP3564R.
Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
Add initialization of `ret` to avoid reports of uninitialized variable
being returned. This variable normally gets initialized while the loop
iterates over channels, but potentially it could be left uninitialized
if the loop finished in its first iteration because of no channels to
be processed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Correct the size of the channel_setup_cfg array, as it should contain
entries for all available channels (AD4130_MAX_CHANNELS), not for the
available configuration slots (AD4130_MAX_SETUPS).
Move also checking of the channel index to the very beginning of
adc_ad4130_channel_setup(), to avoid potential writes to .live_cfg
beyond the channel_setup_cfg array.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for 16-channel ADC to cc23x0 SoC. The driver supports the
following conversion modes:
- Single channel | Single conversion,
- Sequence of channels (up to 4) | Single conversion.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
On nrf54h20 there are additional analog pins (AIN8+). When differential
mode is used they must not be mixed with AIN0-AIN7. Add build time
validation which detects if configuration is invalid.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add it515xx analog to digital converter driver which supports 8 channels
ch0 ~ ch7 and 12-bit resolution.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
Replace occurrences of "RaspberryPi" with "Raspberry Pi" in
documentation, comment blocks etc. Correct the name of "PicoW" to
"Pico W", matching Raspberry Pi's documentation at
https://www.raspberrypi.com/documentation/microcontrollers/pico-series.html .
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Allow STM32 ADC driver to operate with DMA support even when
CONFIG_MEM_ATTR is disabled which happen when CONFIG_ARM_MPU is
intentionally disabled despite the CPU supports MPU.
By the way, remove some #ifdef directive on header files inclusion
that add noise in the header file inclusion section without any
benefit. Also remove inclusion of zephyr/arch/cache.h that is not
needed at all.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Added support for differentail or single ended setup.
Reading resolution form dt - adc spec.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
This commit changes to use ambiq hal power control APIs
to replace the previous register settings to power on
ambiq drivers.
Signed-off-by: Hao Luo <hluo@ambiq.com>
Extend support in dt bindings and in the driver to allow use of
AIN8 to AIN13 analog inputs.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Initial AD405X driver supporting sampling, averaging
and burst averaging operation modes. Configurable
without interrupts or with device ready and
data ready interrupt.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Currently, in Renesas adc driver, channel_count is used
as the maximum index of the channels can be supported.
However, the value input in dts of "channel_count"
represents the total number of supported channels.
After consideration, we have decided to remove this
reduntant property.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Since the RA2L1 uses the macro "ICU_EVENT" instead of
"ELC_EVENT" (which is currently used) to input into
the IELSR register, the ek_ra2l1 board cannot assign
any interrupts for any driver.
This commit aim to correct the Event macro to input correct
value for IELSR register on all the Renesas SoC by using
"BSP_PRV_IELS_ENUM" macro.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
