Commit graph

6012 commits

Author SHA1 Message Date
Jaxson Han
6fc3903bbe arch: arm64: mpu: Fix some minor CHECKIF issues
There are two CHECKIFs whose check condition is wrong.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2023-07-11 15:04:54 +02:00
Mykola Kvach
d0472aae7a soc: arm64: add Renesas Rcar Gen3 SoC support
Add files for supporting arm64 Renesas r8a77951 SoC.
Add config option CPU_CORTEX_A57.

Enable build of clock_control_r8a7795_cpg_mssr.c for
a new ARM64 SoC R8A77951.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2023-07-11 11:17:41 +02:00
Alberto Escolar Piedras
ee268a6d4b posix arch cmake: Add clarification on use of target_link_options
Clarify why we use target_link_options() instead of
target_link_libraries()

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-10 09:51:25 +02:00
Florian Grandel
e256b7d244 kernel: spinlock: LOCKED -> K_SPINLOCK
Let the kernel use the new K_SPINLOCK macro and remove the alias.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-10 09:27:21 +02:00
Alberto Escolar Piedras
265010a4b6 native boards: Make native simulator host trampolines avaliable to all
To ease writing common drivers, let's make the host trampolines
from the native simulator avaliable to all posix based boards.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-07 14:32:41 +02:00
Andrzej Kuros
abd90085ac soc: arm: nrf53: workaround pop lr after wfi crash
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.

This commit inserts additional `nop` instruction after waking up
to delay access to the memory.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-07-07 14:32:27 +02:00
Alberto Escolar Piedras
dadacfaac2 soc (native): Use nce directly from native_simulator
Instead of keeping a replica of the nce code,
now that the native_simulator is in tree, let's use
it directly.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-07 12:54:19 +02:00
Alberto Escolar Piedras
2096006cd8 POSIX arch: Give a nicer error message if built in unsuported platform
Instead of failing badly later, let's give a clear error
message if the user tries to build in an unsupported platform.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-06 14:46:48 +02:00
Alberto Escolar Piedras
ece74b7b7f native_sim: Add new native_sim board
Add the new native_sim board, based on the native simulator.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-05 07:01:19 -04:00
Alberto Escolar Piedras
945429e8c3 arch POSIX: provide a bottom which uses natsim's thread emul
This allows building with embedded libCs in the Zephyr side,
as the POSIX arch bottom is not anymore built in Zephyr context.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-05 07:01:19 -04:00
Alberto Escolar Piedras
41a185a1b5 arch POSIX: Use posix cheats only for native apps
native libraries do not need it

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-05 07:01:19 -04:00
Alberto Escolar Piedras
56dc20eb1d Kconfig: Tidy up dependants of NATIVE_APPLICATION
So they depend or select on the right NATIVE_BUILD
instead of NATIVE_APPLICATION.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-07-05 07:01:19 -04:00
Gerard Marull-Paretas
0d4e5bf67f arch: arm: nmi: simplify NMI initialization
Zephyr provides a default NMI handler (`z_SysNmiOnReset`), which will
basically call `wfi` endlessly. It is allowed to override such handler
when CONFIG_RUNTIME_NMI=y, via `z_arm_nmi_set_handler`. However,
enabling such option also provided `z_arm_nmi_init` (via `NMI_INIT()`),
which basically sets the handler to `DefaultHandler` (a new handler that
basically printks and reboots). This is strictly not needed, and
independent of the runtime NMI option. As a result, most SoCs were
blindly calling `NMI_INIT()`, probably because of a copy&paste effect.
In the majority of cases, this was a no-op, but most SoCs do IRQ
enable/disable, making this even more convoluted. To make things worse,
the init call is expected to run after console has been initialized (for
printk to work?), but most SoCs just called it in PRE_KERNEL_1+0.

This patch just drops this NMI initializer API, and leaves only the
handler set call when CONFIG_RUNTIME_NMI=y.

NMI_INIT() dummy definition is left in this patch to preserve
bisectability, will be dropped later.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-07-05 09:15:36 +02:00
Roberto Medina
6622735ea8 arch: arm64: add support for coredump
* Add support for coredump on ARM64 architectures.
* Add the script used for post-processing coredump output.

Signed-off-by: Marcelo Ruaro <marcelo.ruaro@huawei.com>
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Signed-off-by: Roberto Medina <roberto.medina@huawei.com>
2023-07-03 09:32:26 +02:00
Najumon Ba
b3d78de656 arch: x86: updated acpi config macro
renamed x86 CONFIG_ACPI config macro to CONFIG_x86_ACPI.

Signed-off-by: Najumon Ba <najumon.ba@intel.com>
2023-06-30 17:53:01 +03:00
Gerard Marull-Paretas
33b116407b arch: arm: cortex_m: scb: fix MPU code compilation guards
The implementation of `z_arm_clear_arm_mpu_config` was compiled for all
ARM cores that declare to have an MPU. However, we only want to compile
it if the MPU is actually enabled.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-29 23:46:39 +02:00
Alberto Escolar Piedras
7ee41b8776 soc inf (native): Refactor into a top and bottom
Where the bottom is the only one which interacts with
the host operating system.
And the top the only one that interacts or is aware
of the hosted operating system (Zephyr).

The bottom uses the native simulator CPU
start/stop emulation.
By now we replicate its code as a provisional measure,
until the native simulator becomes standard.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 12:16:26 +02:00
Alberto Escolar Piedras
bd66c1d953 arch POSIX: Refactor into a top and bottom
Where the bottom is the only one which interacts with
the host operating system, and does not necessarily
need to know about the Zephyr OS.
This is in preparation for the native simulator,
which which the bottom is also fully Zephy agnostic.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 12:16:26 +02:00
Alberto Escolar Piedras
78e1d6fa5e arch posix: Set C standard version in arch instead of boards
The issue due to which we set the default compiler C std version
to C11 is not specific to any particular POSIX arch board,
but to all. Instead of setting this property for each board,
let's set it at the architecture level.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 08:59:21 +02:00
Lucas Tamborrino
eb028ccf55 debug: coredump: xtensa: Add esp32s3
Add coredump support for esp32s3.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-21 16:06:06 -04:00
Lucas Tamborrino
ba3766a75f debug: coredump: xtensa: add esp32s2
Add coredump support for esp32s2.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-21 16:06:06 -04:00
Huifeng Zhang
c1ecb8faaa arch: arm: enable FPU and FPU sharing for v8r aarch32
This commit is to enable FPU and FPU_SHARING for v8r aarch32.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
Huifeng Zhang
89ea503b29 arch: arm: Add support for 32 double-precision registers
This adds support for 32 double-precision registers in the context
switching of aarch32 architecture.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
Huifeng Zhang
b0612e14e0 arch: arm: save 'fpscr' in the svc and isr handler
`fpscr` is assigned from `struct __fpu_sf.fpscr` in `vfp_restore`, but it
wasn't saved into `struct __fpu_sf.fpscr` in the svc and isr handler, So
it may be a dirty value.

    - Fix it by saving `fpscr` in the svc hand isr handler.
    - Jump out if FPU isn't enabled

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
Björn Stenberg
234fec579a scripts: gen_relocate_app.py: Give sections unique names
The code_relocation feature creates generic section names that sometimes
conflict with already existing names.

This patch adds a '_reloc_' word to the created names to reduce the risk
of conflict.

This solves #54785.

Signed-off-by: Björn Stenberg <bjorn@haxx.se>
2023-06-20 16:33:49 +02:00
Daniel Leung
97dc67e666 riscv: syscalls: use zephyr_syscall_header
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-06-17 07:57:45 -04:00
Carlo Caione
d395b7f1e8 riscv: Add CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET
Some RISCV platforms shipping a CLIC have a peculiar interrupt ID
ordering / mapping.

According to the "Core-Local Interrupt Controller (CLIC) RISC-V
Privileged Architecture Extensions" Version 0.9-draft at paragraph 16.1
one of these ordering recommendations is "CLIC-mode interrupt-map for
systems retaining interrupt ID compatible with CLINT mode" that is
described how:

  The CLINT-mode interrupts retain their interrupt ID in CLIC mode.
  [...]
  The existing CLINT software interrupt bits are primarily intended for
  inter-hart interrupt signaling, and so are retained for that purpose.
  [...]
  CLIC interrupt inputs are allocated IDs beginning at interrupt ID
  17. Any fast local interrupts that would have been connected at
  interrupt ID 16 and above should now be mapped into corresponding
  inputs of the CLIC.

That is a very convoluted way to say that interrupts 0 to 15 are
reserved for internal use and CLIC only controls interrupts reserved for
platform use (16 up to n + 16, where n is the maximum number of
interrupts supported).

Let's now take now into consideration this situation in the DT:

  clic: interrupt-controller {
    ...
  };

  device0: some-device {
    interrupt-parent = <&clic>;
    interrupts = <0x1>;
    ...
  };

and in the driver for device0:

  IRQ_CONNECT(DT_IRQN(node), ...);

From the hardware prospective:

(1a) device0 is using the first IRQ line of the CLIC
(2a) the interrupt ID / exception code of the `MSTATUS` register
     associated to this IRQ is 17, because the IDs 0 to 15 are reserved

From the software / Zephyr prospective:

(1b) Zephyr is installing the IRQ vector into the SW ISR table (and into
     the IRQ vector table for DIRECT ISRs in case of CLIC vectored mode)
     at index 0x1.
(2b) Zephyr is using the interrupt ID of the `MSTATUS` register to index
     into the SW ISR table (or IRQ vector table)

It's now clear how (2a) and (2b) are in contrast with each other.

To fix this problem we have to take into account the offset introduced
by the reserved interrupts. To do so we introduce
CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET as hidden option for the
platforms to set.

This Kconfig option is used to shift the interrupt numbers when
installing the IRQ vector into the SW ISR table and/or IRQ vector table.
So for example in the previous case and using
CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET == 16, the IRQ vector
associated to the device0 would be correctly installed at index 17 (16 +
1), matching what is reported by the `MSTATUS` register.

CONFIG_NUM_IRQS must be increased accordingly.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-17 07:49:16 -04:00
Carlo Caione
fc480c9382 riscv: privileged: Add support for CLIC vectored mode
Zephyr currently only supports CLINT direct mode and CLINT vectored
mode. Add support for CLIC vectored mode as well.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-17 07:48:52 -04:00
Carlo Caione
6160383ec7 riscv: Rename RISCV_MTVEC_VECTORED_MODE to RISCV_VECTORED_MODE
Before adding support for the CLIC vectored mode, rename
CONFIG_RISCV_MTVEC_VECTORED_MODE to CONFIG_RISCV_VECTORED_MODE to be
more generic and eventually include also the CLIC vectored mode.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-17 07:48:52 -04:00
Dino Li
252d68ff9f arch/riscv: add support for detecting null pointer exception using PMP
This change uses a PMP slot to implement null pointer detection.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2023-06-17 07:45:30 -04:00
Daniel Leung
ad826f3d69 x86: x86_64 can only support max 4 CPUs
With all the stacks and TSS (etc), the x86_64 arch code can only
support maximum of 4 CPUs at the moment. So add a build assert
if more CPUs are specified via CONFIG_MP_MAX_NUM_CPUS, also
overwrite the range value for CONFIG_MP_MAX_NUM_CPUS.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-06-17 07:28:10 -04:00
Carlo Caione
edd3437826 riscv: Rename Kconfig symbol to *_PRIVILEGED
Rename SOC_FAMILY_RISCV_PRIVILEGE to SOC_FAMILY_RISCV_PRIVILEGED because
the spec is "privileged".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-09 11:46:29 -04:00
Evgeniy Paltsev
9d6ced3822 ARC: SMP: fix livelock in thread abort due to exception
We are missing setting of switch_handle for the thread which
is aborting due to exception (i.e. in case of k_panic or
__ASSERT triggered). This may cause livelock in SMP code
after a08e23f68e commit ("kernel/sched: Fix SMP
must-wait-for-switch conditions in abort/join").

Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
2023-06-08 20:27:06 -04:00
Luca Fancellu
c8a9634a30 arch: arm64: Use atomic for fpu_owner pointer
Currently the lazy fpu saving algorithm in arm64 is using the fpu_owner
pointer from the cpu structure to understand the owner of the context
in the cpu and save it in case someone different from the owner is
accessing the fpu.

The semantics for memory consistency across smp systems is quite prone
to errors and reworks on the current code might miss some barriers that
could lead to inconsistent state across cores, so to overcome the issue,
use atomics to hide the complexity and be sure that the code will behave
as intended.

While there, add some isb barriers after writes to cpacr_el1, following
the guidance of ARM ARM specs about writes on system registers.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
2023-06-08 09:35:11 -04:00
Nicolas Pitre
5c7d2f1a90 riscv: exclude more code when multithreading is disabled
This will avoid unconditionally pulling z_riscv_switch() into the build
as it is not used, reducing the resulting binary some more.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-05-31 06:17:10 -04:00
Keith Packard
6ccdf47f60 lib/cpp: Remove CONFIG_CPP_MAIN
With Zephyr now always using `int main(void)`, there's no longer any need
for this definition. The last remaining use which gated the declaration of
_posix_zephyr_main isn't necessary as adding that declaration
unconditionally is harmless.

Signed-off-by: Keith Packard <keithp@keithp.com>
2023-05-31 06:16:35 -04:00
Jaxson Han
08791d5fae arch: arm64: Enable FPU and FPU_SHARING for v8r aarch64
This commit is to enable FPU and FPU_SHARING for v8r aarch64.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2023-05-30 10:14:55 +02:00
Jaxson Han
0b3136c2e8 arch: arm64: Add cpu_map to map cpu id and mpid
cpu_node_list does not hold the corrent mapping of cpu id and mpid when
core booting sequence does not follow the DTS cpu node sequence. This
will cause an issue that sgi cannot deliver to the right target.

Add the cpu_map array to hold the corrent mapping between cpu id and
mpid.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2023-05-30 10:14:55 +02:00
Jaxson Han
f03a4cec57 arch: arm64: Fix the STACK_INIT logic during the reset
Each core should init their own stack during the reset when SMP enabled,
but do not touch others. The current init results in each core starting
init the stack from the same address which will break others.

Fix the issue by setting a correct start address.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2023-05-30 10:14:55 +02:00
Jaxson Han
101ae5d240 arch: arm64: mpu: Remove LOG print before mpu enabled
LOG system has unalignment access instruction which will cause an
alignment exception before MPU is enabled. Remove the LOG print before
MPU is enabled to avoid this issue.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2023-05-30 10:14:55 +02:00
Andy Ross
b89e427bd6 kernel/sched: Rename/redocument wait_for_switch() -> z_sched_switch_spin()
This trick turns out also to be needed by the abort/join code.
Promote it to a more formal-looking internal API and clean up the
documentation to (hopefully) clarify the exact behavior and better
explain the need.

This is one of the more... enchanted bits of the scheduler, and while
the trick is IMHO pretty clean, it remains a big SMP footgun.

Signed-off-by: Andy Ross <andyross@google.com>
2023-05-26 17:09:35 -04:00
Chad Karaginides
9ab7354a46 arch: arm64: SCR_EL3 EEL2 Enablement
For secure EL2 to be entered the EEL2 bit in SCR_EL3 must be set.  This
should only be set if Zephyr has not been configured for NS mode only,
if the device is currently in secure EL3, and if secure EL2 is supported
via the SEL2 bit in AA64PFRO_EL1.  Added logic to enable EEL2 if all
conditions are met.

Signed-off-by: Chad Karaginides <quic_chadk@quicinc.com>
2023-05-26 13:51:50 -04:00
Marek Matej
92b7d37397 arch: riscv: Fix bogus condition
Remove double preprocessor condition.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-05-26 10:36:15 -04:00
Nicolas Pitre
6935ea54d5 Revert "arch: riscv: Enable builds without the multithreading"
This reverts commit f0b458a619.

This is a pointless change that simply increases footprint.
Existing code already supports compilation without multithreading.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-05-26 09:04:30 -04:00
Chad Karaginides
f8b9faff24 arch: arm64: Added ISBs after SCTLR Modifications
Per the ARMv8 architecture document, modification of the system control
register is a context-changing operation. Context-changing operations are
only guaranteed to be seen after a context synchronization event.
An ISB is a context synchronization event.  One has been placed after
each SCTLR modification. Issue was found running full speed on target.

Signed-off-by: Chad Karaginides <quic_chadk@quicinc.com>
2023-05-25 16:33:03 -04:00
Marek Matej
1c130d0060 arch: xtensa: Enable builds without the multithreading
Allow builds which has CONFIG_MULTITHREADING disabled.
This is reduce code footprint which is handy for
constrained targets as bootloaders.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-05-25 16:15:54 +02:00
Marek Matej
f0b458a619 arch: riscv: Enable builds without the multithreading
Allow builds which has CONFIG_MULTITHREADING disabled.
This is reduce code footprint which is handy for
constrained targets as bootloaders.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-05-25 16:15:54 +02:00
Marek Matej
4796746b5e soc: esp32: MCUboot support
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-05-25 16:15:54 +02:00
Carlo Caione
f4cbb01074 barriers: Enable builtin barriers for RISCV
By setting CONFIG_BARRIER_OPERATIONS_BUILTIN.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-25 06:29:03 -04:00
Carlo Caione
637c3ed159 barriers: Enable builtin barriers for POSIX
By setting CONFIG_BARRIER_OPERATIONS_BUILTIN.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-25 11:58:31 +02:00