riscv: smp: prepare for more than one IPI type
Right now this is hardcoded to z_sched_ipi(). Make it so that other IPI services can be added in the future. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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1 changed files with 19 additions and 19 deletions
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@ -8,6 +8,7 @@
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#include <zephyr/kernel.h>
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#include <ksched.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/atomic.h>
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volatile struct {
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arch_cpustart_t fn;
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@ -54,47 +55,46 @@ void z_riscv_secondary_cpu_init(int cpu_num)
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}
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#ifdef CONFIG_SMP
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static uint32_t *get_hart_msip(int hart_id)
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{
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return (uint32_t *)(unsigned long)(RISCV_MSIP_BASE + (hart_id * 4));
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}
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#define MSIP(hartid) ((volatile uint32_t *)RISCV_MSIP_BASE)[hartid]
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static atomic_val_t cpu_pending_ipi[CONFIG_MP_MAX_NUM_CPUS];
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#define IPI_SCHED BIT(0)
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void arch_sched_ipi(void)
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{
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unsigned int key;
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uint32_t i;
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uint8_t id;
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key = arch_irq_lock();
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id = _current_cpu->id;
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unsigned int key = arch_irq_lock();
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unsigned int id = _current_cpu->id;
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unsigned int num_cpus = arch_num_cpus();
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for (i = 0U; i < num_cpus; i++) {
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for (unsigned int i = 0; i < num_cpus; i++) {
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if (i != id && _kernel.cpus[i].arch.online) {
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volatile uint32_t *r = get_hart_msip(_kernel.cpus[i].arch.hartid);
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*r = 1U;
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atomic_or(&cpu_pending_ipi[i], IPI_SCHED);
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MSIP(_kernel.cpus[i].arch.hartid) = 1;
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}
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}
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arch_irq_unlock(key);
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}
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static void sched_ipi_handler(const void *unused)
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static void ipi_handler(const void *unused)
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{
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ARG_UNUSED(unused);
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volatile uint32_t *r = get_hart_msip(csr_read(mhartid));
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*r = 0U;
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MSIP(csr_read(mhartid)) = 0;
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z_sched_ipi();
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atomic_val_t pending_ipi = atomic_get(&cpu_pending_ipi[_current_cpu->id]);
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if (pending_ipi & IPI_SCHED) {
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z_sched_ipi();
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}
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}
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static int riscv_smp_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(RISCV_MACHINE_SOFT_IRQ, 0, sched_ipi_handler, NULL, 0);
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IRQ_CONNECT(RISCV_MACHINE_SOFT_IRQ, 0, ipi_handler, NULL, 0);
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irq_enable(RISCV_MACHINE_SOFT_IRQ);
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return 0;
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