riscv: don't include the secondary CPU boot code when not needed

Linker garbage collection couldn't work due to the explicit reference
in reset.S.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2023-01-06 22:33:35 -05:00 committed by Carles Cufí
commit 96a65e2fc0
2 changed files with 8 additions and 1 deletions

View file

@ -11,10 +11,13 @@ zephyr_library_sources(
reboot.c
reset.S
switch.S
smp.c
thread.c
)
if ((CONFIG_MP_MAX_NUM_CPUS GREATER 1) OR (CONFIG_SMP))
zephyr_library_sources(smp.c)
endif ()
zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S)

View file

@ -97,6 +97,7 @@ aa_loop:
call _PrepC
boot_secondary_core:
#if CONFIG_MP_MAX_NUM_CPUS > 1
la t0, riscv_cpu_wake_flag
lr t0, 0(t0)
bne a0, t0, boot_secondary_core
@ -108,3 +109,6 @@ boot_secondary_core:
la t0, riscv_cpu_wake_flag
sr zero, 0(t0)
j z_riscv_secondary_cpu_init
#else
j loop_unconfigured_cores
#endif