riscv: don't include the secondary CPU boot code when not needed
Linker garbage collection couldn't work due to the explicit reference in reset.S. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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2 changed files with 8 additions and 1 deletions
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@ -11,10 +11,13 @@ zephyr_library_sources(
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reboot.c
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reset.S
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switch.S
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smp.c
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thread.c
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)
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if ((CONFIG_MP_MAX_NUM_CPUS GREATER 1) OR (CONFIG_SMP))
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zephyr_library_sources(smp.c)
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endif ()
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zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S)
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@ -97,6 +97,7 @@ aa_loop:
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call _PrepC
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boot_secondary_core:
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#if CONFIG_MP_MAX_NUM_CPUS > 1
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la t0, riscv_cpu_wake_flag
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lr t0, 0(t0)
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bne a0, t0, boot_secondary_core
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@ -108,3 +109,6 @@ boot_secondary_core:
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la t0, riscv_cpu_wake_flag
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sr zero, 0(t0)
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j z_riscv_secondary_cpu_init
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#else
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j loop_unconfigured_cores
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#endif
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