Commit graph

6,329 commits

Author SHA1 Message Date
Daniel Leung
711622cbba xtensa: remove get_sreg macro from fatal.c
There is no in-file user. So remove it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
004e68ccea xtensa: move exception handling func to arch internal header
z_xtensa_dump_stack() and z_xtensa_exccause() are both arch
internal functions that should not be exposed in public API.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
43b0b48de7 xtensa: move files under core/include/ into include/
Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
d9b34c6108 xtensa: move irq management stuff into irq_manage.c...
... from xtensa_asm2.c. Other architectures have
z_irq_spurious() and *_irq_is_enabled() test in irq_manage.c.
So follow the trend here.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
264391fe88 xtensa: refactor thread related stuff into its own file...
... from xtensa_asm2.c.

Everything has been stuffed inside xtensa_asm2.c where
they are all mangled together. So extract thread related
stuff into its own file.

Note that arch_float_*() may not be thread related but
most other architectures put them into thread.c. So we
also do it here.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
aa64b1f98e xtensa: move arch_spin_relax into smp.c
arch_spin_relax() does not really fit into the scheme of
xtensa_asm2.c as it is mainly about handling interrupts
and exceptions. So move it into smp.c, similar to other
architectures which arch_spin_relax() defined.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
106061b307 xtensa: rename files with hyphens to underscores
Simply to provide some consistencies on file naming under
arch/xtensa.

These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
43990d1c0e xtensa: remove xtensa-asm2.h
xtensa-asm2.h only contains the function declaration of
xtensa_init_stack() which is only used in one file. So
make the actual implementation a static function in that
file. Also there is really no need to expose stack init
function as arch public API. So remove xtensa-asm2.h.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
6694390ac8 xtensa: cleanup Kconfig file
* Wording on CONFIG_SIMULATOR_XTENSA
* Remove "default n" as default is no anyway.
* Remove some tabs as we almost never indent inside a if block
  in Zephyr.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
fc7ef47ed5 xtensa: remove CONFIG_XTENSA_NO_IPC
There is no in-tree user. Also, it is misleading as we use
SCOMPARE1 for spinlock too, not just IPC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung
d17524b86c xtensa: remove CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from arch
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should be defined at the SoC
or the board level since Xtensa cores are high configurable.
The default is just for ISS (Instruction Set Simulator). So
remove it from the arch level.

The xt-sim board is the only one in tree that is targeting
the ISS, so add it there.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Anas Nashif
8e5c3ce616 arch: xtensa: check for xt-clang instead of xcc-clang
Check against new variant name. xcc-clang usage is deprecated.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-12 18:48:14 +00:00
Anas Nashif
e29452da64 arch: arm: remove aarch32 from include header guards
We follow the path of the header to define the guard, aarch32 was
removed some time ago and the guards still had AARCH32 in them, just
remove it and keep the guard consistent and short.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-12 18:47:57 +00:00
Tomasz Bursztyka
daf42fe77a arch/x86: CPUs expose an unimplemented feature
Instruction cache related functions (see include/zephyr/arch/cache.h)
are not implemented in x86, thus let's not set CONFIG_CPU_HAS_ICACHE
which may end up in build failure if one sets CONFIG_ICACHE.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2023-12-12 19:11:13 +01:00
Tomasz Bursztyka
b1cc7312cf arch/x86: Fixing dcache enable/disable code
It did not build in x86_64 due to the fact that cr0 is a 64bits
register in such architecture, instead of being a 32bits one originaly
so the place holder has to follow that size. Such place holder must be
initialized to 0 to make sure no upper 32 bits ends up set which would
conclude in a general protection error.

Operand size specifier (l, q ...) is useless as well in this context.

Clearing up the masks by using proper macros.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2023-12-12 19:11:13 +01:00
Flavio Ceolin
0a7251e365 xtensa: mmu: Fix tlb shootdown
Fix the way we read the current l1 page table set in the mmu.
We use it check if the current page table is different from the
running thread.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-12-12 10:58:03 +01:00
Flavio Ceolin
a19d415c35 xtensa: mmu: Fix xtensa_ptevaddr_get
We use ptevaddr_get to know the address the page table is set.
It happens that for this use, we should just use the ptebase field
of ptevaddr register.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-12-12 10:58:03 +01:00
Flavio Ceolin
7382d7052b xtensa: mmu: Fix partition permission
The ring field in the pte mapping a memory partition should
be based in the partition attribute and not in the domain
asid that is used only to set the ASID (in RASID) position for
user ring.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-12-12 10:57:57 +01:00
Anas Nashif
ae39c3f7d7 arch: arm: z_arm_prep_c -> z_prep_c
Rename to use common naming for z_prep_c applied to all architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:23:52 -05:00
Anas Nashif
fb19d532ed arch: x86: z_x86_prep_c -> z_prep_c
Rename to use common naming for z_prep_c applied to all architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:23:52 -05:00
Anas Nashif
4a73fb1b92 x86: add CODE_UNREACHABLE after z_cstart
Add CODE_UNREACHABLE to be consistent with all other architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:23:52 -05:00
Anas Nashif
5a77fc239f arch: arm: z_arm64_prep_c -> z_prep_c
Rename to use common naming for z_prep_c applied to all architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:23:52 -05:00
Anas Nashif
9f3ed1b2b3 arch: _PrepC -> z_prep_c
Rename to use common naming for z_prep_c applied to all architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:23:52 -05:00
Anas Nashif
552f7194e3 arch: exception: rename header guard
Match guard with header file name.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:22:40 -05:00
Anas Nashif
ca3839ca38 arch: arm64: rename expection header
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:22:40 -05:00
Anas Nashif
699880a430 arch: arm: cortex_m: rename expection header
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:22:40 -05:00
Anas Nashif
4d5fd2edf2 arch: arm: cortex_a_r: rename expection header
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:22:40 -05:00
Anas Nashif
1813a33108 arch: arm: rename expection header
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:22:40 -05:00
Anas Nashif
87eb1d842f arch: arc: rename expection header
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:22:40 -05:00
Sebastian Bøe
3b24ef305f tz: Remove unused trustzone driver
The arm_core_tz.c trustzone driver was developed by Nordic and was
previously used by Nordic, but it is not used by us any more. Since we
stopped using it I can see that it has bit rotted (the include path
for tz.h is not available), so no else has started using it either
evidently.

Remove the broken and dead code.

We keep the HAS_ARM_SAU Kconfig as it is selected by a myriad of
platforms and determines if __SAUREGION_PRESENT is defined. I have
been unable to prove that this define is also unused.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2023-12-11 09:56:08 +01:00
Yong Cong Sin
9bfe6efbb5 arch: common: multilevel irq: verify interrupt level bits configuration
Add `BUILD_ASSERT`s to make sure that the interrupt bits
allocated to each levels are enough to cover the number of
IRQs in each respective level.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Yong Cong Sin
f3da086ac3 arch: common: sw_isr: make sure that the table index is within range
Assert that the `local_irq` of each levels should only ranges
from `0` to `CONFIG_MAX_IRQ_PER_AGGREGATOR`, so that it doesn't
overflow the other aggregators.

Also, assert that the output of `z_get_sw_isr_table_idx` shouldn't
overflow the ISR table.

Update the `sw_isr_table` tests to test the range of
`CONFIG_MAX_IRQ_PER_AGGREGATOR` instead of the entire range of
level bits.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Yong Cong Sin
0274821bb7 arch: common: multilevel irq: move CAT_3RD_LVL_LIST into 3rd level guard
The `CAT_3RD_LVL_LIST` macro is only used when
`CONFIG_3RD_LEVEL_INTERRUPTS` is enabled, so move it into the
compiler guard.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Yong Cong Sin
48d9af46e3 arch: common: multilevel irq: fix issues where the intc device is NULL
The `irq` argument of the `Z_IF_DT_INTC_IRQN_EQ` macro
coincides with the `'irq'` argument passed into the `DT_IRQ`
macro, the former was supposed to be a number, while the latter
is a string/type, together this means that it was intepreted
as:

```c
DT_IRQ(node_id, <some_number>)
```

instead of

```c
DT_IRQ(node_id, irq)
```

as intended, so the macros never managed to match a device with
the IRQ properly, resulting in the `dev` member of the table
being NULL.

Solve this by renaming all the `irq` args in the macros to
`_irq` to avoid mixed usage.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Alberto Escolar Piedras
9323a3f9c7 arch/Kconfig: Fix ARCH_POSIX comment
The comment applies to all POSIX arch based targets,
not just native_posix.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-12-07 10:39:31 +00:00
Dmitrii Golovanov
f308299ca2 debug: gdbstub: kconfig: Add GDBSTUB_TRACE config option
Add GDBSTUB_TRACE config option to extend GDB backend debug logging
for remote commands received and to debug the GDB stub itself.

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
2023-12-06 17:52:18 +00:00
Alberto Escolar Piedras
210bd28a24 native_simulator: Allow to pass extra options for localizing symbols
Some libraries (like Openthread's spinel code) define their
API as externally linkable. This will make those symbols
remain as externally linkable by default after the
Zephyr build has produced the native simulator library
(MCU code).
When building an AMP native_simulator executable with
several MCUs each including these, the linker will see
those symbols as still linkable and duplicated, and
throw an error.

So let's give the option for users/developers of those
libraries to define extra symbols they want
to localize before assembling the final executable.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-12-06 09:25:41 +00:00
Andrei Emeltchenko
2f7021064f arch: x86: pcie: Remove old include
Remove old outdated include, causing build error. The acpi.h is not
needed since it is already included if ACPI is enabled and
INTEL_VTD_ICTL depends on ACPI.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-12-06 09:17:08 +00:00
Wilfried Chauveau
29ffaaa0b6 arch: arm: cortex_m: Remove CPU_HAS_*CACHE from CPU_CORTEX_M7
Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7
definition renders them mandatory.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-05 10:19:15 +00:00
Wilfried Chauveau
a00aa3bcfa arch: arm: cortex_m: add config for PMU
This adds kconfig entries for Performance Monitoring Unit (PMU).

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-05 10:19:15 +00:00
Joakim Andersson
4217920d7c arch: arm: Use returned reason from secure fault handle function
Use the returned reason from the secure fault handle function.
I see no reason why this was ignored, and it is used in the hardfault
handler.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-12-05 10:12:48 +00:00
Guennadi Liakhovetski
03519afb84 llext: xtensa: add support for local symbol relocations
Add support for relocating local symbols, as specified in the
.rela.dyn section.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-12-01 10:08:12 -05:00
Tomasz Bursztyka
17d9275467 arch/x86: Fix building early console driver
io_mapped seems to always exist even though it's not set anywhere, so
testing if it is different to 0 to actually define
UART_IS_IOPORT_ACCESS.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2023-12-01 10:54:59 +00:00
Wilfried Chauveau
85af32e16e arch: arm: remove num-mpu-regions
Remove this property presumably unused.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-01 10:48:00 +00:00
Flavio Ceolin
683accaef0 xtensa: mmu: Include missing header
This file uses inline functions declared in cache.h and consequently
has to include that file.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-11-27 19:57:46 +01:00
Johan Hedberg
084b8e4f97 x86: Only enable EFI_CONSOLE if UART console is not enabled
Most x86 build configurations enable the UART console. Since EFI console
has also defaulted to enabled, this means that the EFI covers the early
part of the boot until UART takes over.

This is all fine, except that enabling EFI console has the effect of
disabling PRINTK_SYNC. This in turn has the effect of causing garbled
output over UART, which has led to several bug reports on x86 platforms
(in particular on up_squared).

Since EFI console should really only be used for early platform bringup
and debugging purposes, it's not really ideal to unconditionally have it
enabled by default. Instead, change the default enabling to be
conditional to the UART console being disabled.

Fixes #54861
Fixes #55071

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2023-11-27 12:19:41 +00:00
Anas Nashif
aed0c451f8 arch: introduce DSP_SHARING and CPU_HAS_DSP configs
introduce global DSP_SHARING and CPU_HAS_DSP to be used by all
architectures and change existing usage in ARC to use those global
configs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-11-27 09:05:54 +00:00
Nikolay Agishev
4cb194f3e8 ARC: MWDT: Force cleanup .device_states section
This PR fixes https://github.com/zephyrproject-rtos/zephyr/issues/64268

MWDT supposes .device_states section as BSS because .device_states
variables defined as uninitialized. This causes the section marked
as NOLOAD section and OpenOCD does not take it in account while
flashing it into board memory.
Finally .device_states variables becomes initialized with garbage
from RAM.

In this PR it's suggested to clean .device_states in early init stage.

Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
2023-11-25 08:48:15 -05:00
Daniel Leung
40ba4015e3 kernel: mm: only include demand_paging.h if needed
This moves including of demand_paging.h out of kernel/mm.h,
so that users of demand paging APIs must include the header
explicitly. Since the main user is kernel itself, we can be
more discipline about header inclusion.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-11-23 10:01:45 +01:00
Joakim Andersson
2ad6dda9fd tfm: Remove limitation of enabling FP when build TF-M NS application
Remove limitation of enabling FP when building TF-M NS application.
FP support have been fixed in the tf-m-tests repository for NS
application.
Board support for NS executable may still be lacking for some boards.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-11-23 10:01:22 +01:00