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5896 commits

Author SHA1 Message Date
Andre Guedes
d95d6c63a1 uart: Introduce QMSI shim driver
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.

This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.

In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y

This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.

Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 23:54:59 +00:00
Juan Manuel Cruz
d151776e59 debug: thread monitor allow to access more thread information
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.

Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.

By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.

It also allows a task to access its kernel task structure
through the first parameter of the thread.

This allows a debugger application to access the information directly
from the thread context structures list.

Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
2016-03-11 22:11:39 +00:00
Andre Guedes
8337953197 Remove unused macro UART_IOAPIC_FLAGS
This patch removes the macro UART_IOAPIC_FLAGS from Quark SE and D2000
soc.h since it is not used anywhere in the code.

Change-Id: I0fd42fac2f02e8617bd92c73c1a0354ef2d7a71a
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 00:15:49 +00:00
Andrew Boie
97594df321 iamcu: fix -fstack-protector
One of the tricks that GCC's stack protector does is to stick a
sentinel value on the stack at the beginning of the function, and
check if it is still there when the function is about to return.
However, since this function switches stacks that fails and we get
a stack protector exception before main() even starts.

Change-Id: I2acba8b8c822d7447d8e371bb72603f36e87f54b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-10 23:28:28 +00:00
Benjamin Walsh
7708710229 Revert "arch: arm: set the architecture via Kconfig"
This reverts commit 3f6884902b.

This commit does not work as intended: the part in arch/arm/Makefile
gets ignored and -mcpu=cortex-m3/4 does not get passed to gcc. It seems
that the zephyr toolchain does not care, but the vxworks assembler
chokes if it is missing, and thinks the CPU does not support thumb ISA

Change-Id: I14d11d3e22dac4952bdab3eb9e2d1c36b1a686c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-03-10 16:31:26 -05:00
Jeff Blais
995a9ba72a arm: K64 SPI module driver
Support for Freescale/NXP K64 SPI modules, limited to:

- Master mode
- A single active set of clock and transfer attributes (CTAR0), which
includes non-adjustable delay parameters
- Tx FIFO fill and Rx FIFO drain interrupt handling
- Standard, continuous select and continuous SCK SPI transfer formats

Also, divide-by-zero code generation in this driver is prevented.
The 'volatile' attribute is added to some of the variables in the baud
rate and delay calculation functions of the K64 SPI driver in order to
prevent bad code generation by gcc toolchains for ARM seen when an
optimization setting above -O0 is used.
Specifically, a register is loaded with the constant 0 and is used as
the divisor in a following divide instruction, resulting in a
divide-by-zero exception.
This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain)
and 5.2.0 (the Zephyr SDK toolchain).

Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 15:50:16 +00:00
Jeff Blais
f428d511f3 arm: config settings for frdm_k64f internal clock dividers
Internal K64 SoC clock dividers were hard-coded. They've been replaced
with config options.

Change-Id: I583307f2e3341525f4445e9ceb89d36634b12802
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 15:50:01 +00:00
Jeff Blais
1f90470a27 arm: K64F Pulse Width Modulation (PWM) support
PWM support using the Freescale K64 FlexTimer Module (FTM)

Change-Id: Iaad429c01bd877babba04e84d6a4679bd7e38120
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 15:49:44 +00:00
Jeff Blais
52b499fd1f arm: Freescale K64/FRDM-K64F Pinmux support
K64 pinmux support is created as a normal driver.

As opposed to the Galileo board, the pin configuration options are
defined by the MCU and are not board-specific.  Separate
platform/board-specific configuration code uses the pinmux driver for
the default pin settings. For FRDM-K64F, only the Arduino pins (22 of a
possible 160) are set up.

Some of the I/O pins routed to the Arduino header are also configured as
JTAG/SWD signals by default and are used by the OpenSDAv2 debug
interface.  Therefore, a PRESERVE_JTAG_IO_PINS config option was created
for the FRDM-K64 platform to prevent the default pin settings from
re-configuring these pins.

The K64 MCU separates pin configuration and control, implemented in the
pinmux driver, from GPIO.  This results in some cross referencing
between the K64 GPIO driver and the K64 pinmux driver due to the
dependencies of one on the other.

This pinmux driver also uses the expanded pinmux function/mode parameter
size to describe pin configuration options with bit fields for the K64,
including up to 8 pin functions, plus interrupt, pullup/down, drive
strength, open-drain and slew rate.

The following GCC warnings in the K64 pinmux driver are prevented when not
compiling with 'no-optimization' (-O0):

warning: 'gpio_dev' may be used uninitialized in this function
[-Wmaybe-uninitialized]

Change-Id: Ie5031d18750143bf895883058b3cd55fd9989fd3
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 11:58:02 +00:00
Jeff Blais
0fd7af2a52 arm: Freescale K64 GPIO driver
Basic driver support for the Freescale K64 GPIO module.

Note that only pin direction, read and write are supported.

Change-Id: I6587bb260197a00497be9ac991002e3dde54718d
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 06:39:16 +00:00
Andrew Boie
4a4e82b0c5 arc: remove CONFIG_SW_ISR_TABLE_BSP
It is semantically identical to CONFIG_SW_ISR_TABLE.

Change-Id: Iff0c47166ee6fb1fd8a0991a67bc863d45c32559
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
d9df4758e4 arc: remove SW_ISR_TABLE_STATIC_CUSTOM
This scenario is no longer supported in code; the Kconfig
didn't actually do anything.

Change-Id: Ic48bffb5180c4f72bc9c5d85cf18b1072432b951
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
e2283a2c58 arc: move vector and sw isr table to core code
Change-Id: Iea7ce4248ff3aaba2a5736c5e50f17c7b8b344af
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
6d972a33cf arm: don't build sw_isr_table if disabled
This table was still being added to ROM even if
CONFIG_SW_ISR_TABLE=n.

Change-Id: Ia0de1349960af1c62e88344b3d5b6655b638219b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
bd7d71efdc arm: remove SW_ISR_TABLE_STATIC_CUSTOM
This config option is no longer implemented and doesn't actually
do anything.

Change-Id: I57ab7ba688f57da21f8a58f62ea37dc6b8daaf18
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
5415d945f8 arm: move irq_vector_table to common location
We don't support hard-coding vectors in this table anymore.
If someone really wants to do this, they can set
IRQ_VECTOR_TABLE_CUSTOM and define their own.

Change-Id: I45f49782ba5fefb0a02eab02ec96efd0019bc6d5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Dmitriy Korovkin
41e55f13ad Kconfig: CPU_MIGHT_SUPPORT_CLFLUSH removal.
Remove CPU_MIGHT_SUPPORT_CLFLUSH as excessive.

Removal the flag requires adding per-SoC cnfiguration,
as some Quark models support clflush instruction, but
some do not, even on compiler level.

Change-Id: I655cba00c629db55d1813c199a2fe08b2d60ef4f
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-03-07 20:25:22 +00:00
Dmitriy Korovkin
287d16d83f x86: Fix cache flush code dependencies
Rearrange the source code in order to place functions
depending on clflush support detection into the proper
section.

Removed dependency between CACHE_LINE_SIZE_DETECT and
CLFLUSH_INSTRUCTION_SUPPORTED or CONFIG_CLFLUSH_DETECT.

Change-Id: I62ba5199763ed16c71f1d2fa372f6cc99b303e6a
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-03-07 20:25:22 +00:00
Daniel Leung
e643cede3a uart: add ISR callback mechanism for UART drivers
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.

Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.

This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.

Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.

This also addresses the following issues:

() UART driver for Atmel SAM3 currently does not support interrupts.
   So remove the code from vector table. This will be updated when
   there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.

This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).

Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-05 13:37:57 +00:00
Dan Kalowsky
3f6884902b arch: arm: set the architecture via Kconfig
Currently the build system has hardcoded values for the -march/-mcpu
which identify what architecture should be used when compiling ARM code.
For processors such as the STM32 this will need to be defined by a per
SOC process.

Change-Id: Ia8158cd687d8d0432ea420e204bb2bc67d33a054
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-03-04 15:08:40 +00:00
Yannis Damigos
baddeadda1 arch: & kernel: Updated Kconfigs to remove errors in html generation
This patch updates some help sections to remove the "ERROR:
Unexpected indentation" messages during hmtl documentation
generation.

Change-Id: Idcdc17727b921b6145f9eb28d85975ceca273ce2
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2016-03-04 13:26:15 +00:00
Anas Nashif
2ed89a49ee rtc: enable clock-gating for RTC on Quark SE
Clockgating was disabled for RTC and disabling RTC had no
effect on Quark SE boards.

Change-Id: I67448d5582a206fc7a68d763d504e9f743043b53
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-29 16:53:36 +00:00
Ido Yariv
744f4fba3d QEMU: Fix the pin2irq translation function
ia32/soc.h is only used by QEMU, but QEMU's INTx routing does not follow
the "standard design consideration".
Instead, the pins are swizzled based on the PCI slot. They are then
routed to IRQs based on the PIIX PIRQ configuration.

For simplicity use hard-coded values for the PIIX PIRQ configuration,
though it may be desirable in the future to determine these dynamically.

Also change the number of PCI buses to 1 and remove irrelevant comments.

Change-Id: I1592009a43dd8a9c5a7c54788fba52f14687ba35
Signed-off-by: Ido Yariv <ido@wizery.com>
2016-02-26 17:05:30 +00:00
Andrew Boie
e444825ee3 irq: formalize external zephyr interrupt API
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.

Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.

Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-26 15:53:22 +00:00
Daniel Leung
1d88a8618d arc: remove defaults for IRQ priority levels
The deleted defaults cannot be overriden by defaults defined
in SoC's Kconfig file. The number of IRQ priority level was
always one, and this caused some code to be dropped within
the fast IRQ handling code. When the electrons aligned in
certain way, undesired effects were observed (e.g. exception,
faults, etc.) when regular IRQs were mixed with fast IRQs.

Moreover, ARC cores are high configurable on hardware level.
So let the SoC config define these values instead.

Change-Id: I2a338d2efc814c46b0f68ab100fc0f66ae0fb60c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-26 15:20:10 +00:00
Benjamin Walsh
fd1aa8575b x86: move reboot via RST_CNT from galileo to generic x86
That implementation is not galileo-specific, but rather a generic way of
rebooting an x86 target. Needs SoC support.

Change-Id: I9c3374a8ab57a624d9d9b7090260c5b11fe4e773
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-25 16:52:27 +00:00
Andre Guedes
536d6ec396 i2c: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/i2c/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.

It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.

Change-Id: If3c260b9a2fa095de47a99eb7fa5b947efefe9b1
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-24 14:34:24 -03:00
Andre Guedes
1eaaa6434b spi: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/spi/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.

It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.

Change-Id: Ic992749b3210ed8a2e454edece41ceca5edbaf2e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-24 14:26:23 -03:00
Andre Guedes
55e93f203c gpio: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/gpio/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.

It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.

Change-Id: Id00f7907fa55025011dabce6e282a9623be23831
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-24 17:05:52 +00:00
Tomasz Bursztyka
16cbf0ea97 quark_se_ss: Add default SPI configuration values
Base address registers and IRQs are set in Kconfig.
Set proper SPI default to various quark_se_ss based boards.

Change-Id: Iadaae551f441457bef334f94f68cafa7c3e499d0
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-20 15:39:16 +00:00
Tomasz Bursztyka
ec678375a3 spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.

Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
 - centralize common macros and definitions into spi_dw.h
 - have a specific spi_dw_quark_se_ss_reg.h for register map, clock
   gating and register helpers dedicated to Quark SE SS.
 - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.

GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.

Adding proper interrupt masks to quark_se_ss soc.h file as well.

One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.

Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.

Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
  handler, but it does not harm doing it anyway and because Quark SE SS
  requires to clear up interrupt as soon as they have been handled,
  introducing a clear_interrupts() function called at the and of the ISR
  handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
  might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
  masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.

Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-20 15:39:16 +00:00
Andre Guedes
424cd841e2 spi: Enable QMSI driver for Quark D2000
This patch fixes the QMSI SPI shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in spi_qmsi_init() because the macro QM_SPI_MST_1
and the function qm_spi_master_1_isr are not defined in QMSI headers
from Quark D2000.

Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.

Change-Id: Ic6e2f7f5a2c3f350ddf360b23ffab6b812948572
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 14:57:45 +00:00
Andre Guedes
2a1871f405 watchdog: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/watchdog/Kconfig because 1) most
of the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).

For Quark D2000, the IRQ priority options (WDT_DW_IRQ_PRI and WDT_QMSI_
IRQ_PRI) values are set to '0' since the priority information is ignored
by the interrupt registering system (the interrupt vectors are fixed in
this SoC).

Change-Id: I8f36c0f0e56211cdee3f2c6fc90c7dcac0a1b5aa
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 14:20:33 +00:00
Andre Guedes
055d775be6 rtc: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/rtc/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).

For Quark D2000, the RTC_IRQ_PRI default value is set to '0' since the
priority information is ignored by the interrupt registering system
(the interrupt vectors are fixed in this SoC).

Change-Id: I70de889cfd22e65f0e7acf7e57ddc6439f028394
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 14:20:32 +00:00
Vinicius Costa Gomes
0e60f325f8 gpio: qmsi: Fix overwriting name set by the driver's Kconfig
The name already set by the driver's Kconfig is correct, so overriding
it only causes confusion.

Change-Id: Ia6405786fdfdf103c922517c8140a07a9de387e0
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-20 14:18:36 +00:00
Andre Guedes
2b608b1e59 gpio: Enable QMSI driver for Quark D2000
This patch fixes the GPIO QMSI shim driver so we are able to use it in
Quark D2000 based platforms. To enable this driver we have to add a few
 #if guards because some macros and functions (e.g. QM_AON_GPIO_0 and
qm_aon_gpio_isr_0) are not defined in QMSI headers from Quark D2000
(this SoC doesn't support the Always-On GPIO controller).

This patch also adds the QMSI driver default options to arch/x86/soc/
quark_d2000/Kconfig.

Change-Id: Ia16a345e1de3008f167ed66f891834607c05f4a2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 13:04:34 +00:00
Vinicius Costa Gomes
821212c3df drivers: gpio: Add support for AON GPIO to QMSI driver
This adds support to the AON GPIO controller using the QMSI driver.

In order to enable it, the following configuration options must be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH TO LIBQMSI"
CONFIG_GPIO_QMSI=y
CONFIG_GPIO_QMSI_AON=y

Change-Id: I5a1a232d97741ad7fdbf40d8aea5a835e5b4e724
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-20 13:02:49 +00:00
Daniel Leung
fb84242956 x86/quark_se: don't start ARC if reset vector is NULL
This adds a NULL check against the reset vector for ARC.
If the reset vector is null, do not start the ARC core
as there is nothing to execute, and will probably cause
the whole SoC to stall.

Change-Id: I78d77b3e5940a205e05c13369f889cf9c5955487
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-20 12:59:07 +00:00
Andre Guedes
6b23dc40d1 watchdog: Set DW driver as default for Quark SE and D2000
This patch changes both Quark SE and D2000 Kconfig files to enable the
WDT_DW driver by default if the WATCHDOG is enabled. This way, we keep
it consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).

Change-Id: I9d8b81c0e659b1408137deb71e33dacf6d4108c2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:52:35 +00:00
Andre Guedes
a4cf537d65 rtc: Set DW driver as default for Quark SE and D2000
This patch changes both Quark SE and D2000 Kconfig files to enable the
RTC_DW driver by default if the RTC is enabled. This way, we keep it
consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).

Change-Id: I4910e501c105b6218d046080c47b1e7a42eced92
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:52:00 +00:00
Andre Guedes
ec7c6a80fc i2c: Enable QMSI driver for Quark D2000
This patch fixes the QMSI I2C shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in i2c_qmsi_init() because the macro QM_I2C_1
is not defined in QMSI headers from Quark D2000.

Since this drivers is now properly tested with Quark D2000, this patch
sets the QMSI driver default options in arch/x86/soc/quark_d2000/Kconfig.
It also adds the wiring information required to test the i2c_lsm9ds0
sample app in the Quark D2000 CRB.

Change-Id: I4be03c09304da5a66ac663e48b1d72225eb5651d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:51:49 +00:00
Andre Guedes
fa1e56520b qmsi: Enable both I2C controllers by default
In case the I2C_QMSI driver is selected by the user, enable both I2C
contollers by default. This is the default behavior for I2C_DW driver
as well.

Change-Id: If3dc8eb0a266fde7f598f7b12370e5be903aafed
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:51:19 +00:00
Benjamin Walsh
74cd948ed3 x1000/pci: fix coding standards
Always use braces, even on one-line code blocks.

Change-Id: Ic9e60db7f851d2fbee5bfd79cd810df23c0c5db0
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-17 21:51:57 +00:00
Ramesh Thomas
3888735e0d adv_power:Advanced Power Management APIs
This is part of an ongoing development of power management
support in zephyr. This implementation builds upon an existing
hook interface and adds more enhancements. This was tested
with reference implementations on quark_d2000 and quark_se.

Change-Id: I28092b7ec90ce1f1cc661cf99ca88708910c8eb2
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-02-12 11:20:32 -08:00
Ramesh Thomas
72e248b11b adv_power:Rename PM functions according to coding convention
Renamed functions and labels used in power management code
according to coding convention.  Only doing this to relevant
functions and not touching functions that will be removed in
future patches.

The stack used during resume would be necessary so
renamed that too.

Change-Id: I2f09a349b0f0fd6520c11b4cd73f4c8e1a13f100
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-02-12 10:57:51 -08:00
Ramesh Thomas
c1a2523445 adv_power:Fix build error when ADVANCED_IDLE flag is enabled
GlobalTss is not defined anywhere. This was originally designed
to be used by power management code to switch thread context to
kernel resume location. An alternative to this method would be
implemented.

Change-Id: I9ae14ba14f9573d8bd8579869cdee9cf85a5684a
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-02-12 10:57:51 -08:00
Sergio Rodriguez
4dee326306 tickless idle x86: Tickless idle support on nanokernel for x86
Modifications to timer drivers and interrupt setup, to manage
the tickless idle for the x86 architecture

Change-Id: Ie02d484b7e5636de6ea382ba2eeed57e704c8498
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
2016-02-11 19:10:24 +00:00
Andrew Boie
f21ff23310 x86: add debug function to dump IDT
Looking at the IDT in a debugger is confusing, add a pretty-printing
function.

Change-Id: Iacc5e204e5d11e3e875c75ddf6d2e2e80b230299
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-10 16:02:17 +00:00
Andrew Boie
313ed31253 x86: fix IDT entry definition
It was, in a nutshell, wrong. Fortunately, the incorrectly
specified fields weren't being used by anything.

Change-Id: I0fa63fa16a267502744a7a2c82865c7de8b5446e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-10 16:01:26 +00:00
Andrew Boie
4455ee6d87 ARM: rebase available priority levels to 0
We have a new policy: users should not be able to configure
an interrupt with "forbidden" priority levels, and any priority
levels with special semantics will be activated by flags.

Change-Id: I757c19cfedcb1d0938eaf4da348ddafb71b3e001
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-08 21:47:35 -05:00