The current gpio_dw_initialize implementation masks the interruptions in the line
dw_write(base_addr, INTMASK, ~(0)) to assign api functions and initialize
interrupt vectors and handlers safely. Immediately after this, the driver expects
that gpio_dw_unmask_int(port) unmasks the interrupts. Without this patch that
implementation is empty for the quark se ss board.
Change-Id: Iac84c8807fcadad8c256c3fcaa4ff624b6337bf3
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Warning comes during compilation about missing prompt, this sets
the prompt for this SoC.
Change-Id: If8b422d6a870eb99c219ab872924875eb04fba0c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is a generic Atom configuration that can be inherited by boards
with Atom SoC like the minnowboard.
Change-Id: I06ab999062be7811d14755fd34440dee8f8b81ed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
No need for the same SoC configuration with different names. Use IA32
as the "SoC" for qemu_x86 "boards".
Change-Id: Iee00538701c5ece14d0c3df637b0aaa54790f0e2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Using LOAPIC Timer as default since it is the default for most target
X86 systems.
Change-Id: I71c9b307839ebcf46fb28e1b709089de600af83f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Previous it was renamed in favor of Qemu, now that we have board support
we move this to the original name and derive a qemu board out of the
platform.
Change-Id: Ia8769b27defa0a39503ecf2e6ec7fc6304b6ff49
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We had one pinmux per platform with support for multiple boards.
This moves pinmuxing to boards as first step. Common functions that
are exposed by the API need to be moved to driver while keeping the
muxing configuration with the boards.
Change-Id: I2b4fabf663db98d644abcb5d51ba83adc6f74541
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo pinmux configuration and reboot code belong into
the board and not the SoC.
Change-Id: If862178569438a8901902088bd085275416c25ef
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define boards based on platforms/SoCs and define them under boards/.
Also unify the naming of all platform, SoC and board files and use
platform.h for platforms and board.h for boards.
Change-Id: Icfeb96479ab5800aca98c80a79bdc3cecd645314
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo board is based on the X1000 SoC, so move galileo to
boards and create this SoC instead, inheriting all SoC related code
and configuration items.
Change-Id: I9b39f1b44644775ee48acae284b82bae7876fffb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
According to the schematic, SPI1_M_ should be properly mapped out
on the pinmux. This should enable the SPI1_M functionality on the
Arduino / Genuino 101 board now.
Change-Id: Ided0147e7c2d835aa58fdc5860e7ca7f55d9e566
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Updating the pinmux to use a local static table for each pin select
option. Instead moving to a static series of function calls that
move the data from the RAM section to the ROM section.
This impacts only the Quark D2000 and the Quark SE chips. It does
not show any impact to the basic_minuteia tests.
All said we see small changes that amount to some values like:
test platform ram_%_change rom_%_change
======================== ============ ============ ============
microkernel:footprint-max quark_se-x86 -0.01 0.0
microkernel:footprint-reg quark_se-x86 -0.02 -0.01
microkernel:footprint-min quark_se-x86 -0.07 -0.02
nanokernel:footprint-max quark_se-x86 -0.02 -0.01
nanokernel:footprint-max quark_d2000 -0.01 -0.01
nanokernel:footprint-reg quark_se-x86 -0.03 -0.01
nanokernel:footprint-reg quark_d2000 -0.02 -0.02
nanokernel:footprint-min quark_se-x86 0.04 0.01
nanokernel:footprint-min quark_d2000 -0.07 -0.04
Change-Id: Ib69403eced60a8c784887dca9dd1954ce73a3e70
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Currently the Quark SE and Quark D2000 platform are only included
through the use of a compile fence one level higher in the Makefile.
Adding in a secondary compile fence to ensure if that check ever
changes, we won't be in trouble.
Change-Id: I5e39faffb4289f80901c0264a50a3e770db3388a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Initial import of the pinmux configuration for the Quark_D2000 series
boards. Some minor tweaking of default values may be needed depending
upon expected usage scenarios.
Change-Id: I3b22219546a6534c7c695d0917a35f6f46b03cf1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adding support for the pinmux pins to set the pullup and input enable
registers. On the Arduino_101 board some pullup pins specifically can
be used to cause a reset for the Arduino sketch being run. Its use on
other pins is currently being investigated.
Change-Id: Id3293a4da84ea5bf553bf62ccb12782cb88503a5
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Naming convention should follow the IP_noun_verb concept. In this case,
renaming several functions from (for example) pinmux_set_pin to
pinmux_pin_set, while also correctly naming the function to their
specific tasks.
This is being done to make way for the ability to change the input
value, pullup value, and the slew as well.
Change-Id: Iec6f1723a48f80b66f3cea44df9bb6925972f6af
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Extending the public interface of the pinmux to allow the end user
to set a pin as an input/output and to pull up the value on
a specified pin.
Change-Id: Ie0a3b6432dd8c7d7a02f32e3d22049bdd99f1410
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
First step for adding the new board layer. Create configurations for the
various boards we support on x86 under boards with the new Kconfig variables
defining them.
The board selection is optional, that means you will be able to run
make menuconfig
and create your own .config and select any SoC.
Change-Id: If08e88e9675d13f0f0501ef6750b9424b15f5dc8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This variable (CONFIG_BOARD) will store the textual form of the
platform name and will be used for locating files related to the
board in the source tree.
Change-Id: I3c8a05ed428451a6785799a5492f0dd14682f208
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allow usage of alternative drivers and do not hardcode drivers
to zephyr own implementation.
Change-Id: Ieb55b5dc88b3643f276b7c48facef7f1c1c42fa7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The LCD display is an add-on, not a feature of the platform or the
board.
Set the defaults and remove the definition from Galileo Kconfig.
Change-Id: Ic319cd765d2dc1fe08cc65615680821fe9bc6a83
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On Arduino 101, the sensor subsystem also has access to the two UARTs
on board. So this adds the necessary code to enable them to be used.
However, one needs to make sure only one core has access to one UART
at the same time.
Change-Id: I9f6c203916164d1b48559a9752fb1e4d879d7fa4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
1. Need to unmask interrupts for the sensor subsystem.
2. The GPIO controllers need their clock enabled before they can
start sending out interrupts.
3. Setting up ISR on ARC requires usage of irq_connect().
Change-Id: I633b07292f11e5c5e768fc51fabb70769d407609
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The interrupt number for GPIO0/GPIO1 are 20 and 21 respectively.
The old value of 8 refers to the interrupts line on the x86 side
of GPIO controller.
Change-Id: I2e9e061d3506e27cb7b14e0431c3b6201a50aad4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The pin mux for Galileo Gen2 isn't set properly to enable UART0_RXD input from
the Arduino headers. EXP1's pin0 OE_N needs to be set HIGH to make the IO0
buffer an Input.
Change-Id: I0167f11ff5ee87bd5afe17300807b1aa4ed17abf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: David Antler <david.a.antler@intel.com>
The argument to 'lidt' is a chunk of memory with the base address
and limit of the IDT, and not the IDT itself. Horrible things
were happening when the IDT itself was being passed to this
instruction.
To be extra safe, disable interrupts while we modify the table
and subsequently reload it.
Change-Id: I9bf96f13a5f6e1be80d11bbfb9db3df1f2ed613a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The code to poke the system integration module to disable clock gating
for UARTs only works for UART0-3 since all the bits are in the same
register. However, clocks for UART4 and UART5 are controlled by
another register. This means that we have been writing to the wrong
bit for enabling UART4.
This patch fixes this issue, and moves the clock gating clock into
board initialization. The incorrect code has also been removed to
prevent accidental mis-use. The dev_data struct is no longer needed
for uart_k20, so that is removed as well.
Change-Id: I67845a417e43647bf0ffcbdbda34ce68fa887713
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Hardware initialization for fsl_frdm_k64f has to be done at the very
beginning at boot, before anything else. So change the init priority
for hardware initialization to 0. This makes sure the hardware is
initialized. Or else any memory/register access will hang
the board.
Change-Id: Idc1c9449bb7cd1ec7b8d8f44004ea76cc7c09a18
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add support for compilers conforming to the IAMCU calling convention
as documented by
https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf
Change-Id: I6fd9d5bede0538b2049772e3850a5940c5dd911e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
All of these stubs at the end pop the stack and tell the LOAPIC
that we are at EOI. Put this in common code which falls through to
_IntExit(). Saves 8 bytes per static IRQ stub. There is also small
constant savings in the common code for dynamic IRQs.
Change-Id: If17e9f105928a4251a2cb3fc0d192649c1c4d84b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Quark SE Lakemont core has a hardware bug where the LOAPIC does
not properly notify the IOAPIC to clear the IRR bit for level-
triggered interrupts.
This patch introduces a workaround where the vector ID of the
in-service interrupt is manually written to the IOAPIC_EOI
register, resulting in the bit being cleared.
Unfortunately, in the context where EOI happens it's very difficult
to identify which IRQ line is being serviced, so this is done
unconditionally for all interrupts vectors whether they are registered
in the IOAPIC RTE table or not.
Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of having two config options to specify interrupt triggering
conditions, merge them into one option and clarify. This is now
similar to other drivers which have interrupt triggers.
Change-Id: I4e60c8c45a08d005dcc8256cb89e4c5be7c94307
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: I89090181acb5f48dd797e7773ab65c5f3d46c42a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: Ie7262b69226ebffa7e1b9e35725fda24b3fe089f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: I2d50457a45fae62ff085f7239712d580243253bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: Ia0a069464392714f38037841de52e8d265fa4f49
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The APIC by default uses vector 0xFF for the spurious interrupt
vector as described in the x86 CPU manual volume 3 section 10.9.
Make this its own config option defaulting to 32.
MVIC doesn't have a spurious interrupt vector, and due to the
fixed IRQ-to-vector mapping for this controller, continue
to use the last available entry.
Change-Id: I29bd09df700629dc0d15b30a6ae590b0df1ef890
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was only needed for an older implementation of software interrupts,
now superseded by the irq_offload() API (which doesn't interact with
the interrupt controller at all)
Change-Id: I8aa696d370ae1799872f6d70de69f3cb5b47456a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
To many people, IPI connotes inter-processor interrupts on SMP
systems. Rename this to IPM, or Inter-Processor Mailboxes.
Change-Id: I032815e23c69a8297c0a43992132441c240fb71e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
define CONFIG_PLATFORM only once in arch/Kconfig and set it
for every platform.
Change-Id: I8554bb36d2d15c3ee71fa63dfc3a763ebca956ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
excecptions are handled the same for i386_sysV_abi and iamcu calling
conventions ATM since we do not have any exceptions that we can
recover from there is no reason to have seperate implementations.
Change-Id: Ica8b332d7756a91b56f7080ac74771ad25d32753
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Add null definitions for the interrupt latency measurement API so we
can remove compile fences in C code.
Change-Id: If86eedf79afcb49002108814dd4fb864956eb667
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
