This moves the STM32 based boards (Nucleo F103RB and STM32 Mini A15) to
the "new" pinmux model.
Change-Id: I190df271a6b83fafeec0b281cd4ee7cf13d7e7db
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Setting the direction of a GPIO pin is not the responsibility of the
pinmux "board" initialisation. This should be left for the GPIO
utilising application.
Some macros that were only used when setting the pin direction are
removed.
Change-Id: I5b63d52446a27fe539c89f0639a8dcadf5ea9f80
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This patch replaces all occurrences of DEV_* codes by errno.h codes at
the arch layer.
Change-Id: I1a1ab6d0481f3660ad032e2690d2577245fe1f34
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
CONFIG_PWM is set to "no" by default, so there is no need
to do it in the SoC kconfig file. Also, setting CONFIG_PWM
there causes kconfig to think that CONFIG_PWM depends on
CONFIG_SOC_FSL_FRDM_K64F and gives warnings about
unmet dependencies if the certain combinations of CONFIG
are set.
Change-Id: I0028accfc4b585dcfa87e0d5733b789691a598e3
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This makes this board more consistent with the rest of the code base.
Change-Id: I5641c6358e638a3585d2154e67d3536b11436e01
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Use of `ldr` triggers unaligned memory access when loading SVC
instruction to r0. This is caused by the fact that SVC is a 16-bit
instruction, hence with a 2 byte offset, we are performing an non-word
aligned access. Prevent this by using `ldrh` to load a halfwords rather
than full words.
Change-Id: Ieae60c2ce86c6cfe15c89627d3a450797ce7e714
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add support for use of HSE (incorrectly named PREDIV1)as input of PLL,
along with HSE bypass for stabilized external clock, and XTPRE
prescaler. Update PLL handling so that we do not unnecessarily enable
PLL clocks, instead enabling only the clocks sources that are required
as per user's configuration.
This change allows higher SYSCLK clock values, up to 72MHz.
Change-Id: Ia7c2be3ce11ac0de2efa664b20e7ab5fddd57a51
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add mapping of registers for embedded flash controller.
Change-Id: I81f891551124e9f124ff59dfe0b3c737ec5b3b63
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Before moving pinmux related code to 'drivers/pinmux' fix their return
codes to be consistent with the rest of the API.
Change-Id: Ie84f64e93745d44bef8b9d2119f6a05cdc8cb8c4
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Add a driver for Independent Watchdog (IWDG) commonly found in STM32
MCUs. The driver has been tested on STM32F1 family MCU.
Change-Id: Idc6ac35990e46901a206b4af0ce3767eb4875de9
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add necessary integration for supporting interrupts on GPIO input pins
for STM32F1 line of MCUs.
Change-Id: I0526a85cc3fdb96891c93ba4840ef27d613ab31b
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add mapping of Alternate Function I/O (AFIO) registers for STM32F1 MCU.
Change-Id: Id3e12290d6869c1f0506549f21407b3cd80d0a64
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Introcuce a driver for External Interrupt/Event Controller (EXTI) found
on STM32 MCUs.
Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add a list of symbolic constants for IRQ lines available on
STM32F1 line of MCUs.
Change-Id: Iebf1847719c0db31cf852529fe5876e3cabbfe52
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add necessary integration code enabling use of common STM32 pinmux
driver.
The alternate function listing currently consists of USART1 pins
only. The listing should be updated when support for more devices is
added.
Change-Id: Ic65aeea9df9aaea7636ecdd6996f56e6ef59dc2f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add functions required for integration with common STM32 GPIO driver.
Change-Id: Ic6637e991f5c0cf659f3b927ed47ef482b13b64f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
() Moves the Quark SE clock control into its submenu.
() Fixes the dependencies in the SoC default Kconfig
so the options are not displayed out of place in
menuconfig.
Change-Id: Ifdf06242be8ceed03c2c657c942875a5a7f2750e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Make kconfig look the same for all architectures.
JIRA: ZEP-107
Change-Id: Ia8100194ec333fc07a1dff4f6f90364ce8bef4d3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The patch adds a driver for STM32F10x series RCC (Reset and Clock
Control) subsystem.
The module is primarily responsible for setting up of MCU's clock
tree. In particular the driver sets up SYSCLK, PLL (with source
configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this
functionality, the subsystem can enable/disable clock signal for
particular peripherals, thus reducing the power consumption of the MCU.
The driver implements clock control driver API. However, subsystem IDs
being HW specific are exposed in driver public header that must be
included by callers. The driver registers a single device using a common
name STM32_CLOCK_CONTROL_NAME. The device is initialized at
the PRIMARY level with priority 1. This allows the initialization to
take place right after SoC initialization routine.
The driver depends on selection of SOC_STM32F1X config option and is MCU
specific.
Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
The patch introduces a new family of SoCs based on STMicroelectronics'
STM32 MCU line. The patch introduces a basic arch/arm/soc layout along
with configuration of 2 MCUs from STM32F1 series: STM32F103VE and
STM32F103RB.
The patch assumes that other MCUs from STM32 family will be included
under arch/arm/soc/st_stm32 tree, to achieve the following layout:
arch/
arm/
soc/
st_stm32/
stm32f0/
stm32f1/
stm32f2/
...
stm32l0/
Most of the configuration within a single MCU family (ex. STM32F1) is
shared, however individual MCUs differ with respect to SRAM size, flash
size or the number of available peripherals. The patch assumes that per
MCU line Kconfig.soc.family file should introduce basic setup for given
series. This can be further tuned by per MCU files, with
Kconfig.soc.stm32f103rb and Kconfig.soc.stm32f103ve as examples.
Each family defines a configuration option, ex. CONFIG_STM32F10X, while
individual MCUs define a corresponding per MCU config options,
ex. CONFIG_STM32F103VE.
From the menuconfig perspective, the user is presented with a family
selection under General Platform Configuration/SoC Selection. A
specific MCU model can be selected by accessing General Platform
Configuration/STM32F1x MCU Selection, with the default entry being
selected by the board configuration.
Change-Id: I22e4defd4a08ed1b2e2cad0e214b34f565e08831
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
This makes sure the CONFIG_GPIO_K64F_* kconfig options have correct
dependencies. Or else CONFIG_GPIO_K64F can be disabled, but all
the CONFIG_GPIO_K64F_{A,B,C,D,E} are enabled.
Same goes for SPI, FTM and pinmux.
Change-Id: I8d225dea714081b14b19006d61b8f3f6afafa5ee
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC selections for each architecture are moved to the top level
in menuconfig and xconfig. This makes it more intuitive to select
architecture -> SoC -> then board, avoiding an additional trip to
go into the architecture menu to select SoC.
Change-Id: I57a78a09adfc4bb12423915b6ad14ceb74381a2b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It makes no sense to allow enabling support for floating point
registers when the CPU has no FPU.
Change-Id: If51187033fc84957721d87fa6e79ef31124f4b14
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
These options should be selected by individual SoC automatically,
and should not be visible options. Or else it would be possible to
select Quark SoCs and telling Kconfig it is from Atom family (which
is incorrect).
Change-Id: I17a6cf713378333e0e7942aa49b381b5eb9526b5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When building with IAMCU, make sure we set the soft-float, otherwise
build would fail with unsupported instruction errors.
JIRA: ZEP-103
Change-Id: I7a5f107a2df50799a7f6dd4aba36c1a977c1461d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The nmi_on_reset.S functions are used by all ARM platforms. It
makes no sense to repeat the same code for all platforms. Moving
the code from each SOC implementation to arch/arm/core.
The same treatment for the NMI_INIT() macro. Moving it from a per
SOC implementation to the include/arch/arm/cortex_m/nmi.h.
Change-Id: I574d8880a44046cc7b9e1b635e80d6e83657b8c1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This creates the QMSI comparator driver which is simply a shim driver
based on the comparator driver provided by QMSI BSP.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_AIO_COMPARATOR=y
CONFIG_AIO_QMSI_COMPARATOR=y
Origin of the file: Original
Change-Id: Iad01cb80f7bb1eff1710cd76cd0afeb70c311e04
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This patch extends the UART QMSI driver so it supports the IRQ APIs from
include/uart.h. The IRQ APIs are enabled by the 'CONFIG_UART_INTERRUPT_
DRIVEN' option.
Differently from others APIs such as I2C and SPI, the UART API is very
low level. For that reason, the IRQ facilities (e.g. irq based transfers)
from the QMSI driver are not useful to the shim driver at the moment. In
order to implement the IRQ APIs we rely on UART registers defined by QMSI.
QMSI UART header is missing some macro definitions from IRR register so
we define them in the shim driver.
Since the IRQ trigger condition is not configurable in the QMSI shim
driver, this patch also changes drivers/serial/Kconfig so the "UART
IRQ Trigger Condition" choice doesn't appear on the menu if the QMSI
driver is selected.
Change-Id: Idf9a0f6a47af2a550a31f474d721068dca989713
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.
This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y
This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.
Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.
Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.
By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.
It also allows a task to access its kernel task structure
through the first parameter of the thread.
This allows a debugger application to access the information directly
from the thread context structures list.
Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
This patch removes the macro UART_IOAPIC_FLAGS from Quark SE and D2000
soc.h since it is not used anywhere in the code.
Change-Id: I0fd42fac2f02e8617bd92c73c1a0354ef2d7a71a
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
One of the tricks that GCC's stack protector does is to stick a
sentinel value on the stack at the beginning of the function, and
check if it is still there when the function is about to return.
However, since this function switches stacks that fails and we get
a stack protector exception before main() even starts.
Change-Id: I2acba8b8c822d7447d8e371bb72603f36e87f54b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This reverts commit 3f6884902b.
This commit does not work as intended: the part in arch/arm/Makefile
gets ignored and -mcpu=cortex-m3/4 does not get passed to gcc. It seems
that the zephyr toolchain does not care, but the vxworks assembler
chokes if it is missing, and thinks the CPU does not support thumb ISA
Change-Id: I14d11d3e22dac4952bdab3eb9e2d1c36b1a686c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Support for Freescale/NXP K64 SPI modules, limited to:
- Master mode
- A single active set of clock and transfer attributes (CTAR0), which
includes non-adjustable delay parameters
- Tx FIFO fill and Rx FIFO drain interrupt handling
- Standard, continuous select and continuous SCK SPI transfer formats
Also, divide-by-zero code generation in this driver is prevented.
The 'volatile' attribute is added to some of the variables in the baud
rate and delay calculation functions of the K64 SPI driver in order to
prevent bad code generation by gcc toolchains for ARM seen when an
optimization setting above -O0 is used.
Specifically, a register is loaded with the constant 0 and is used as
the divisor in a following divide instruction, resulting in a
divide-by-zero exception.
This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain)
and 5.2.0 (the Zephyr SDK toolchain).
Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Internal K64 SoC clock dividers were hard-coded. They've been replaced
with config options.
Change-Id: I583307f2e3341525f4445e9ceb89d36634b12802
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
PWM support using the Freescale K64 FlexTimer Module (FTM)
Change-Id: Iaad429c01bd877babba04e84d6a4679bd7e38120
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
K64 pinmux support is created as a normal driver.
As opposed to the Galileo board, the pin configuration options are
defined by the MCU and are not board-specific. Separate
platform/board-specific configuration code uses the pinmux driver for
the default pin settings. For FRDM-K64F, only the Arduino pins (22 of a
possible 160) are set up.
Some of the I/O pins routed to the Arduino header are also configured as
JTAG/SWD signals by default and are used by the OpenSDAv2 debug
interface. Therefore, a PRESERVE_JTAG_IO_PINS config option was created
for the FRDM-K64 platform to prevent the default pin settings from
re-configuring these pins.
The K64 MCU separates pin configuration and control, implemented in the
pinmux driver, from GPIO. This results in some cross referencing
between the K64 GPIO driver and the K64 pinmux driver due to the
dependencies of one on the other.
This pinmux driver also uses the expanded pinmux function/mode parameter
size to describe pin configuration options with bit fields for the K64,
including up to 8 pin functions, plus interrupt, pullup/down, drive
strength, open-drain and slew rate.
The following GCC warnings in the K64 pinmux driver are prevented when not
compiling with 'no-optimization' (-O0):
warning: 'gpio_dev' may be used uninitialized in this function
[-Wmaybe-uninitialized]
Change-Id: Ie5031d18750143bf895883058b3cd55fd9989fd3
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Basic driver support for the Freescale K64 GPIO module.
Note that only pin direction, read and write are supported.
Change-Id: I6587bb260197a00497be9ac991002e3dde54718d
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
It is semantically identical to CONFIG_SW_ISR_TABLE.
Change-Id: Iff0c47166ee6fb1fd8a0991a67bc863d45c32559
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This scenario is no longer supported in code; the Kconfig
didn't actually do anything.
Change-Id: Ic48bffb5180c4f72bc9c5d85cf18b1072432b951
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This table was still being added to ROM even if
CONFIG_SW_ISR_TABLE=n.
Change-Id: Ia0de1349960af1c62e88344b3d5b6655b638219b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This config option is no longer implemented and doesn't actually
do anything.
Change-Id: I57ab7ba688f57da21f8a58f62ea37dc6b8daaf18
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We don't support hard-coding vectors in this table anymore.
If someone really wants to do this, they can set
IRQ_VECTOR_TABLE_CUSTOM and define their own.
Change-Id: I45f49782ba5fefb0a02eab02ec96efd0019bc6d5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Remove CPU_MIGHT_SUPPORT_CLFLUSH as excessive.
Removal the flag requires adding per-SoC cnfiguration,
as some Quark models support clflush instruction, but
some do not, even on compiler level.
Change-Id: I655cba00c629db55d1813c199a2fe08b2d60ef4f
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
