Commit graph

1902 commits

Author SHA1 Message Date
Andrew Boie
6b58e2c0a3 x86: use large VM size if ACPI
We've already enabled full RAM mapping if ACPI is enabled, also
set a large 3GB address space size, these systems are not RAM-
constrained (they are PC platforms) and they have large MMIO
config spaces for PCIe.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-26 16:21:50 -05:00
Andrew Boie
77861037d9 x86: map all RAM if ACPI
ACPI tables can lurk anywhere. Map all memory so they can be
read.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie
ed22064e27 x86: implement demand paging APIs
All arch_ APIs and macros are implemented, and the page fault
handling code will call into the core kernel.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie
299a2cf62e mmu: arch_mem_map() may no longer fail
Pre-allocation of paging structures is now required, such that
no allocations are ever needed when mapping memory.

Instantiation of new memory domains may still require allocations
unless a common page table is used.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie
b0b7756756 x86: pre-allocate address space
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.

We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.

The default address space size is now 8MB, but this can be
tuned by the application.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie
5c47bbc501 x86: only map the kernel image
The policy is changed and we no longer map all page frames.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie
f3e9b61a91 x86: reserve the first megabyte
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie
69355d13a8 arch: add KERNEL_VM_OFFSET
This is only needed if the base address of SRAM doesn't
have the same alignment as the base address of the virtual
address space.

Fix the calculations on X86 where this is the case.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Kumar Gala
895277f909 x86: Fix zefi.py creating valid images
When zefi.py was changed to pass compiler and objcopy the flag to
objcopy for the EFI target was dropped.  This is because the current
SDK (0.12.1) doesn't support that target type for objcopy.  However,
target is necessary for the images to be created correctly and boot.

Switch back to use the host objcopy as a stop gap fix, until the SDK
can support target for EFI.

Fixes: #31517

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-01-22 12:41:27 -05:00
Daniel Leung
4e8abfcba7 x86: use TSC for timing information
This changes the timing functions to use TSC to gather
timing information instead of using the timer for
scheduling as it provides higher resolution for timing
information.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-01-22 11:05:30 -05:00
Anas Nashif
6f61663695 Revert "arch: add KERNEL_VM_OFFSET"
This reverts commit fd2434edbd.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Anas Nashif
4422b1d376 Revert "x86: reserve the first megabyte"
This reverts commit 51e3c9efa5.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Anas Nashif
83d15d96e3 Revert "x86: only map the kernel image"
This reverts commit 3660040e22.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Anas Nashif
e980848ba7 Revert "x86: pre-allocate address space"
This reverts commit 64f05d443a.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Anas Nashif
a2ec139bf7 Revert "mmu: arch_mem_map() may no longer fail"
This reverts commit db56722729.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Anas Nashif
adff757c72 Revert "x86: implement demand paging APIs"
This reverts commit 7711c9a82d.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Daniel Leung
d3218ca515 debug: coredump: remove z_ prefix for stuff used outside subsys
This removes the z_ prefix those (functions, enums, etc.) that
are being used outside the coredump subsys. This aligns better
with the naming convention.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-01-21 22:08:59 -05:00
Andrew Boie
7711c9a82d x86: implement demand paging APIs
All arch_ APIs and macros are implemented, and the page fault
handling code will call into the core kernel.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Andrew Boie
db56722729 mmu: arch_mem_map() may no longer fail
Pre-allocation of paging structures is now required, such that
no allocations are ever needed when mapping memory.

Instantiation of new memory domains may still require allocations
unless a common page table is used.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Andrew Boie
64f05d443a x86: pre-allocate address space
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.

We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.

The default address space size is now 8MB, but this can be
tuned by the application.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Andrew Boie
3660040e22 x86: only map the kernel image
The policy is changed and we no longer map all page frames.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Andrew Boie
51e3c9efa5 x86: reserve the first megabyte
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Andrew Boie
fd2434edbd arch: add KERNEL_VM_OFFSET
This is only needed if the base address of SRAM doesn't
have the same alignment as the base address of the virtual
address space.

Fix the calculations on X86 where this is the case.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Daniel Leung
ff720cd9b3 x86: enable soft float support for Zephyr SDK
This adds the correct compiler and linker flags to
support software floating point operations. The flags
need to be added to TOOLCHAIN_*_FLAGS for GCC to find
the correct library (when calling GCC with
--print-libgcc-file-name).

Note that software floating point needs to be turned
on for Newlib. This is due to Newlib having floating
point numbers in its various printf() functions which
results in floating point instructions being emitted
from toolchain. These instructions are placed very
early in the functions which results in them being
executed even though the format string contains
no floating point conversions. Without using CONFIG_FPU
to enable hardware floating point support, any calls to
printf() like functions will result in exceptions
complaining FPU is not available. Although forcing
CONFIG_FPU=y with newlib is an option, and because
the OS doesn't know which threads would call these
printf() functions, Zephyr has to assume all threads
are using FPU and thus incurring performance penalty as
every context switching now needs to save FPU registers.
A compromise here is to use soft float instead. Newlib
with soft float enabled does not have floating point
instructions and yet can still support its printf()
like functions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-01-20 16:45:31 -05:00
Spoorthy Priya Yerabolu
513b9f598f zefi.py: Use cross compiler while building zephyr
Currently, zefi.py takes host GCC OBJCOPY as
default. Fixing the script to use CMAKE_C_COMPILER
and CMAKE_OBJCOPY.

Fixes: #27047

Signed-off-by: Spoorthy Priya Yerabolu <spoorthy.priya.yerabolu@intel.com>
2021-01-20 16:38:12 -05:00
Carlo Caione
dc4cc5565b x86: cache: Use new cache APIs
Add an helper to correctly use the new cache APIs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-01-19 14:31:02 -05:00
Carlo Caione
20f59c8f1e cache: Rename CACHE_FLUSHING to CACHE_MANAGEMENT
The new APIs are not only dealing with cache flushing. Rename the
Kconfig symbol to CACHE_MANAGEMENT to better reflect this change.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-01-19 14:31:02 -05:00
Carlo Caione
923b3be890 kconfig: Unify CACHE_* options
The kconfig options to configure the cache flushing framework are
currently living in the arch-specific kconfigs of ARC and X86 (32-bit)
architectures even though these are defining the same things.

Move the common symbols in one place accessible by all the architectures
and create a menu for those.

Leave the default values in the arch-specific locations.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-01-19 14:31:02 -05:00
Johan Hedberg
c88dae574c x86: early_serial: Suppress output attempts prior to init
Until now, any attempts to call printk prior to early serial init has
caused page faults due to the device not being mapped yet. Add static
variable to track the pre-init status, and instead of page faulting
just suppress the characters and log a warning right after init to
give an indication that output characters have been lost.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-15 11:01:23 -05:00
Flavio Ceolin
28cf88183a x86: power: Remove dead code
X86 currently has no support for deep sleep states, just removing this
dead code.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-08 06:49:43 -05:00
Daniel Leung
0aa61793de x86: remove custom switch to main thread function
The original idea of using a custom switch to main thread
function is to make sure the buffer to save floating point
registers are aligned correctly or else exception would be
raised when saving/restoring those registers. Since
the struct of the buffer is defined with alignment hint
to toolchain, the alignment will be enforced by toolchain
as long as the k_thread struct variable is a dedicated,
declared variable. So there is no need for the custom
switch to main thread function anymore.

This also allows the stack usage calculation of
the interrupt stack to function properly as the end of
the interrupt stack is not being used for the dummy
thread anymore.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-01-04 16:59:59 -08:00
Kumar Gala
63d0a109c0 arch/x86: Convert DEVICE_AND_API_INIT to DEVICE_DEFINE
Convert device to DEVICE_DEFINE instead of DEVICE_AND_API_INIT
so we can deprecate DEVICE_AND_API_INIT in the future.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-12-20 10:19:30 -06:00
Johan Hedberg
8b01efe8e6 arch: x86: Fix early_serial build error when using fixed MMIO address
Fix the following complilation error that happens when specifying a
fixed MMIO address for the UART through X86_SOC_EARLY_SERIAL_MMIO8_ADDR:

arch/x86/core/early_serial.c:30:26: error: #if with no expression
   30 | #if DEVICE_MMIO_IS_IN_RAM

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-17 11:55:50 -05:00
Andrew Boie
d2ad783a97 mmu: rename z_mem_map to z_phys_map
Renamed to make its semantics clearer; this function maps
*physical* memory addresses and is not equivalent to
posix mmap(), which might confuse people.

mem_map test case remains the same name as other memory
mapping scenarios will be added in the fullness of time.

Parameter names to z_phys_map adjusted slightly to be more
consistent with names used in other memory mapping functions.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-16 08:55:55 -05:00
Andrew Boie
0a791b7a09 x86: mmu: clarify physical/virtual conversions
The page table implementation requires conversion between virtual
and physical addresses when creating and walking page tables. Add
a phys_addr() and virt_addr() functions instead of hard-casting
these values, plus a macro for doing the same in ASM code.

Currently, all pages are identity mapped so VIRT_OFFSET = 0, but
this will now still work if they are not the same.

ASM language was also updated for 32-bit. Comments were left in
64-bit, as long mode semantics don't allow use of Z_X86_PHYS_ADDR
macro; this can be revisited later.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-15 14:16:51 -05:00
Anas Nashif
3d33d767f1 twister: rename in code
Some code had reference to sanitycheck, replace with twister.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-12-11 14:13:02 -05:00
Kumar Gala
7defa02329 x86: Fix compiler warning in z_x86_dump_mmu_flags
Fix compiler warnings associated with 'level' and 'entry' variables
'may be used uninitialized in this function'

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-12-11 17:41:58 +02:00
Andrew Boie
3605832682 x86: fix z_x86_thread_page_tables_get()
This was reporting the wrong page tables for supervisor
threads with KPTI enabled.

Analysis of existing use of this API revealed no problems
caused by this issue, but someone may trip over it eventually.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-10 18:22:58 -05:00
Andrew Boie
905e6d52a7 x86: improve page table printouts
We now show:

 - Data pages that are paged out in red
 - Pages that are mapped but non-present due to KPTI,
   respectively in cyan or blue if they are identity mapped
   or not.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-10 18:22:58 -05:00
Andrei Emeltchenko
34573803a8 arch: x86_64: Rename _exception_stack to z_x86_exception_stack
Rename stack name according to MISRA-C standard.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-12-10 17:06:17 +02:00
Andrei Emeltchenko
a4dbb51e74 arch: x86_64: Rename _nmi_stack to z_x86_nmi_stack
Rename stack name according to MISRA-C standard.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-12-10 17:06:17 +02:00
Andrei Emeltchenko
ddc5139a6e arch: x86_64: Trivial correction
Correct register name in comment.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-12-10 17:06:17 +02:00
Andrei Emeltchenko
e7d3dd1362 arch: x86_64: Using right exception stack with KPTI
With kernel page table isolation (KPTI) we cannot use right exception
stack since after using trampoline stack there was always switch to
7th IST stack (__x86_tss64_t_ist7_OFFSET). Make this configurable as a
parameter in EXCEPT(nr, ist) and EXCEPT_CODE(nr, ist). For the NMI we
would use ist6 (_nmi_stack).

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-12-10 17:06:17 +02:00
Andrei Emeltchenko
85db42883f arch/x86: Use NMI stack for NMIs
NMI can be triggered at any time, even when in the process of
switching stacks. Use special stack for it.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-12-10 17:06:17 +02:00
Andrei Emeltchenko
8db06aee69 arch/x86: Add NMI registration API
Add simple NMI registration API.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-12-10 17:06:17 +02:00
Andrew Boie
39dab07f49 x86: provide inline pentry_get()
Non-debug code may need this functionality, create an inline.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-09 16:57:01 -08:00
Andrew Boie
d362acb567 x86: mmu: add PTE_LEVEL
For code clarity, add a macro indicating the paging level
for leaf page tables.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-09 16:57:01 -08:00
Andrew Boie
d7dc0deae5 x86: mmu: fix ipi comments
Delete an incorrect one and note a limitation of the current
IPI implementation.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-09 16:57:01 -08:00
Andrew Boie
e20846eaa7 x86: mmu: add range_map_unlocked()
range_map() now doesn't implicitly hold x86_mmu_lock, allowing
callers to use it if the lock is already held.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-09 16:57:01 -08:00
Andrew Boie
6eabe20aee x86: mmu: fix typo
Fix incorrect macro name in comment.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-09 16:57:01 -08:00