llext: Full ARM ELF relocation support
Adds support for all relocation type produced by GCC on ARM platform using partial linking (-r flag) or shared link (-fpic and -shared flag). Signed-off-by: Cedric Lescop <cedric.lescop@se.com>
This commit is contained in:
Cedric Lescop
Anas Nashif
parent
00b46686b1
commit
7b1d9d6166
4 changed files with 366 additions and 58 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2023 Intel Corporation
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* Copyright (c) 2024 Schneider Electric
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -11,42 +12,266 @@
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LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL);
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#define ARM_BL_BLX_UPPER_S_BIT BIT(10)
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#define ARM_BL_BLX_ADDEND_OFFSET 0
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#define ARM_BL_BLX_ADDEND_SIZE 11
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#define ARM_BL_BLX_ADDEND_MASK 0x7FF
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#define ARM_BL_BLX_HDR_MASK 0xF800
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#define ARM_BL_BLX_LOWER_T1T2_BIT BIT(12)
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#define OPCODE2ARMMEM(x) ((uint32_t)(x))
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#define OPCODE2THM16MEM(x) ((uint16_t)(x))
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#define MEM2ARMOPCODE(x) OPCODE2ARMMEM(x)
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#define MEM2THM16OPCODE(x) OPCODE2THM16MEM(x)
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#define JUMP_UPPER_BOUNDARY ((int32_t)0xfe000000)
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#define JUMP_LOWER_BOUNDARY ((int32_t)0x2000000)
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#define PREL31_UPPER_BOUNDARY ((int32_t)0x40000000)
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#define PREL31_LOWER_BOUNDARY ((int32_t)-0x40000000)
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#define THM_JUMP_UPPER_BOUNDARY ((int32_t)0xff000000)
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#define THM_JUMP_LOWER_BOUNDARY ((int32_t)0x01000000)
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#define MASK_V4BX_RM_COND 0xf000000f
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#define MASK_V4BX_NOT_RM_COND 0x01a0f000
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#define MASK_BRANCH_COND GENMASK(31, 28)
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#define MASK_BRANCH_101 GENMASK(27, 25)
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#define MASK_BRANCH_L BIT(24)
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#define MASK_BRANCH_OFFSET GENMASK(23, 0)
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#define MASK_MOV_COND GENMASK(31, 28)
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#define MASK_MOV_00 GENMASK(27, 26)
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#define MASK_MOV_I BIT(25)
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#define MASK_MOV_OPCODE GENMASK(24, 21)
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#define MASK_MOV_S BIT(20)
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#define MASK_MOV_RN GENMASK(19, 16)
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#define MASK_MOV_RD GENMASK(15, 12)
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#define MASK_MOV_OPERAND2 GENMASK(11, 0)
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#define BIT_THM_BW_S 10
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#define MASK_THM_BW_11110 GENMASK(15, 11)
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#define MASK_THM_BW_S BIT(10)
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#define MASK_THM_BW_IMM10 GENMASK(9, 0)
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#define BIT_THM_BL_J1 13
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#define BIT_THM_BL_J2 11
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#define MASK_THM_BL_10 GENMASK(15, 14)
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#define MASK_THM_BL_J1 BIT(13)
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#define MASK_THM_BL_1 BIT(12)
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#define MASK_THM_BL_J2 BIT(11)
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#define MASK_THM_BL_IMM11 GENMASK(10, 0)
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#define MASK_THM_MOV_11110 GENMASK(15, 11)
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#define MASK_THM_MOV_I BIT(10)
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#define MASK_THM_MOV_100100 GENMASK(9, 4)
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#define MASK_THM_MOV_IMM4 GENMASK(3, 0)
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#define MASK_THM_MOV_0 BIT(15)
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#define MASK_THM_MOV_IMM3 GENMASK(14, 12)
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#define MASK_THM_MOV_RD GENMASK(11, 8)
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#define MASK_THM_MOV_IMM8 GENMASK(7, 0)
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#define SHIFT_PREL31_SIGN 30
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#define SHIFT_BRANCH_OFFSET 2
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#define SHIFT_JUMPS_SIGN 25
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#define SHIFT_MOV_RD 4
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#define SHIFT_MOV_RN 4
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#define SHIFT_MOVS_SIGN 15
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#define SHIFT_THM_JUMPS_SIGN 24
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#define SHIFT_THM_BW_IMM10 12
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#define SHIFT_THM_BL_J2 22
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#define SHIFT_THM_BL_J1 23
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#define SHIFT_THM_MOVS_SIGN 15
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#define SHIFT_THM_MOV_I 1
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#define SHIFT_THM_MOV_IMM3 4
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#define SHIFT_THM_MOV_IMM4 12
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static int32_t arm_bl_blx_decode_addend(uintptr_t opaddr)
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static inline int prel31_decode(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name, int32_t *offset)
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{
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uint16_t upper = *((uint16_t *)opaddr);
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uint16_t lower = *(((uint16_t *)opaddr) + 1);
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int ret;
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int32_t addend = upper & ARM_BL_BLX_UPPER_S_BIT ? UINT32_MAX : 0;
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*offset = sign_extend(*(int32_t *)loc, SHIFT_PREL31_SIGN);
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*offset += sym_base_addr - loc;
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if (*offset >= PREL31_UPPER_BOUNDARY || *offset < PREL31_LOWER_BOUNDARY) {
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LOG_ERR("sym '%s': relocation out of range (%#x -> %#x)\n",
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sym_name, loc, sym_base_addr);
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ret = -ENOEXEC;
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} else {
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ret = 0;
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}
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addend <<= ARM_BL_BLX_ADDEND_SIZE;
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addend |= upper & ARM_BL_BLX_ADDEND_MASK;
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addend <<= ARM_BL_BLX_ADDEND_SIZE;
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addend |= lower & ARM_BL_BLX_ADDEND_MASK;
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return lower & ARM_BL_BLX_LOWER_T1T2_BIT ? addend << 1 : addend << 2;
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return ret;
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}
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static void arm_bl_blx_encode_addend(uintptr_t opaddr, int32_t addend)
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static inline void prel31_reloc(uint32_t loc, int32_t *offset)
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{
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uint16_t upper = *((uint16_t *)opaddr);
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uint16_t lower = *(((uint16_t *)opaddr) + 1);
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*(uint32_t *)loc &= BIT(31);
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*(uint32_t *)loc |= *offset & GENMASK(30, 0);
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}
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addend = upper & ARM_BL_BLX_UPPER_S_BIT ? addend >> 1 : addend >> 2;
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static int prel31_handler(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name)
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{
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int ret;
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int32_t offset;
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upper &= ARM_BL_BLX_HDR_MASK;
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lower &= ARM_BL_BLX_HDR_MASK;
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upper |= (addend >> ARM_BL_BLX_ADDEND_SIZE) & ARM_BL_BLX_ADDEND_MASK;
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lower |= addend & ARM_BL_BLX_ADDEND_MASK;
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ret = prel31_decode(reloc_type, loc, sym_base_addr, sym_name, &offset);
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if (!ret) {
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prel31_reloc(loc, &offset);
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}
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*((uint16_t *)opaddr) = upper;
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*(((uint16_t *)opaddr) + 1) = lower;
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return ret;
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}
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static inline int jumps_decode(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name, int32_t *offset)
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{
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int ret;
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*offset = MEM2ARMOPCODE(*(uint32_t *)loc);
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*offset = (*offset & MASK_BRANCH_OFFSET) << SHIFT_BRANCH_OFFSET;
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*offset = sign_extend(*offset, SHIFT_JUMPS_SIGN);
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*offset += sym_base_addr - loc;
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if (*offset >= JUMP_LOWER_BOUNDARY || *offset <= JUMP_UPPER_BOUNDARY) {
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LOG_ERR("sym '%s': relocation out of range (%#x -> %#x)\n",
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sym_name, loc, sym_base_addr);
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ret = -ENOEXEC;
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} else {
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ret = 0;
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}
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return ret;
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}
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static inline void jumps_reloc(uint32_t loc, int32_t *offset)
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{
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*offset >>= SHIFT_BRANCH_OFFSET;
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*offset &= MASK_BRANCH_OFFSET;
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*(uint32_t *)loc &= OPCODE2ARMMEM(MASK_BRANCH_COND|MASK_BRANCH_101|MASK_BRANCH_L);
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*(uint32_t *)loc |= OPCODE2ARMMEM(*offset);
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}
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static int jumps_handler(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name)
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{
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int ret;
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int32_t offset;
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ret = jumps_decode(reloc_type, loc, sym_base_addr, sym_name, &offset);
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if (!ret) {
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jumps_reloc(loc, &offset);
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}
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return ret;
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}
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static void movs_handler(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name)
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{
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int32_t offset;
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uint32_t tmp;
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offset = tmp = MEM2ARMOPCODE(*(uint32_t *)loc);
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offset = ((offset & MASK_MOV_RN) >> SHIFT_MOV_RN) | (offset & MASK_MOV_OPERAND2);
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offset = sign_extend(offset, SHIFT_MOVS_SIGN);
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offset += sym_base_addr;
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if (reloc_type == R_ARM_MOVT_PREL || reloc_type == R_ARM_MOVW_PREL_NC) {
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offset -= loc;
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}
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if (reloc_type == R_ARM_MOVT_ABS || reloc_type == R_ARM_MOVT_PREL) {
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offset >>= 16;
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}
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tmp &= (MASK_MOV_COND | MASK_MOV_00 | MASK_MOV_I | MASK_MOV_OPCODE | MASK_MOV_RD);
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tmp |= ((offset & MASK_MOV_RD) << SHIFT_MOV_RD) | (offset & MASK_MOV_OPERAND2);
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*(uint32_t *)loc = OPCODE2ARMMEM(tmp);
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}
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static inline int thm_jumps_decode(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name, int32_t *offset,
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uint32_t *upper, uint32_t *lower)
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{
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int ret;
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uint32_t j_one, j_two, sign;
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*upper = MEM2THM16OPCODE(*(uint16_t *)loc);
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*lower = MEM2THM16OPCODE(*(uint16_t *)(loc + 2));
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/* sign is bit10 */
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sign = (*upper >> BIT_THM_BW_S) & 1;
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j_one = (*lower >> BIT_THM_BL_J1) & 1;
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j_two = (*lower >> BIT_THM_BL_J2) & 1;
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*offset = (sign << SHIFT_THM_JUMPS_SIGN) |
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((~(j_one ^ sign) & 1) << SHIFT_THM_BL_J1) |
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((~(j_two ^ sign) & 1) << SHIFT_THM_BL_J2) |
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((*upper & MASK_THM_BW_IMM10) << SHIFT_THM_BW_IMM10) |
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((*lower & MASK_THM_BL_IMM11) << 1);
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*offset = sign_extend(*offset, SHIFT_THM_JUMPS_SIGN);
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*offset += sym_base_addr - loc;
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if (*offset >= THM_JUMP_LOWER_BOUNDARY || *offset <= THM_JUMP_UPPER_BOUNDARY) {
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LOG_ERR("sym '%s': relocation out of range (%#x -> %#x)\n",
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sym_name, loc, sym_base_addr);
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ret = -ENOEXEC;
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} else {
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ret = 0;
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}
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return ret;
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}
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static inline void thm_jumps_reloc(uint32_t loc, int32_t *offset,
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uint32_t *upper, uint32_t *lower)
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{
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uint32_t j_one, j_two, sign;
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sign = (*offset >> SHIFT_THM_JUMPS_SIGN) & 1;
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j_one = sign ^ (~(*offset >> SHIFT_THM_BL_J1) & 1);
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j_two = sign ^ (~(*offset >> SHIFT_THM_BL_J2) & 1);
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*upper = (uint16_t)((*upper & MASK_THM_BW_11110) | (sign << BIT_THM_BW_S) |
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((*offset >> SHIFT_THM_BW_IMM10) & MASK_THM_BW_IMM10));
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*lower = (uint16_t)((*lower & (MASK_THM_BL_10|MASK_THM_BL_1)) |
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(j_one << BIT_THM_BL_J1) | (j_two << BIT_THM_BL_J2) |
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((*offset >> 1) & MASK_THM_BL_IMM11));
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*(uint16_t *)loc = OPCODE2THM16MEM(*upper);
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*(uint16_t *)(loc + 2) = OPCODE2THM16MEM(*lower);
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}
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static int thm_jumps_handler(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name)
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{
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int ret;
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int32_t offset;
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uint32_t upper, lower;
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ret = thm_jumps_decode(reloc_type, loc, sym_base_addr, sym_name, &offset, &upper, &lower);
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if (!ret) {
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thm_jumps_reloc(loc, &offset, &upper, &lower);
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}
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return ret;
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}
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static void thm_movs_handler(elf_word reloc_type, uint32_t loc,
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uint32_t sym_base_addr, const char *sym_name)
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{
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int32_t offset;
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uint32_t upper, lower;
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upper = MEM2THM16OPCODE(*(uint16_t *)loc);
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lower = MEM2THM16OPCODE(*(uint16_t *)(loc + 2));
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/* MOVT/MOVW instructions encoding in Thumb-2 */
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offset = ((upper & MASK_THM_MOV_IMM4) << SHIFT_THM_MOV_IMM4) |
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((upper & MASK_THM_MOV_I) << SHIFT_THM_MOV_I) |
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((lower & MASK_THM_MOV_IMM3) >> SHIFT_THM_MOV_IMM3) | (lower & MASK_THM_MOV_IMM8);
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offset = sign_extend(offset, SHIFT_THM_MOVS_SIGN);
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offset += sym_base_addr;
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if (reloc_type == R_ARM_THM_MOVT_PREL || reloc_type == R_ARM_THM_MOVW_PREL_NC) {
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offset -= loc;
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}
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if (reloc_type == R_ARM_THM_MOVT_ABS || reloc_type == R_ARM_THM_MOVT_PREL) {
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offset >>= 16;
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}
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upper = (uint16_t)((upper & (MASK_THM_MOV_11110|MASK_THM_MOV_100100)) |
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((offset & (MASK_THM_MOV_IMM4<<SHIFT_THM_MOV_IMM4)) >> SHIFT_THM_MOV_IMM4) |
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((offset & (MASK_THM_MOV_I<<SHIFT_THM_MOV_I)) >> SHIFT_THM_MOV_I));
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lower = (uint16_t)((lower & (MASK_THM_MOV_0|MASK_THM_MOV_RD)) |
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((offset & (MASK_THM_MOV_IMM3>>SHIFT_THM_MOV_IMM3)) << SHIFT_THM_MOV_IMM3) |
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(offset & MASK_THM_MOV_IMM8));
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*(uint16_t *)loc = OPCODE2THM16MEM(upper);
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*(uint16_t *)(loc + 2) = OPCODE2THM16MEM(lower);
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}
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/**
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@ -58,32 +283,81 @@ static void arm_bl_blx_encode_addend(uintptr_t opaddr, int32_t addend)
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*
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* The relocation codes for arm are well documented
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* https://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst#relocation
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*
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* Handler functions prefixed by '_thm_' means that they are Thumb instructions specific.
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* Do NOT mix them with not 'Thumb instructions' in the below switch/case: they are not
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* intended to work together.
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*/
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void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval)
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int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr,
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const char *sym_name, uintptr_t load_bias)
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{
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int ret = 0;
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elf_word reloc_type = ELF32_R_TYPE(rel->r_info);
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LOG_DBG("%d %lx %lx %s", reloc_type, loc, sym_base_addr, sym_name);
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switch (reloc_type) {
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case R_ARM_NONE:
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break;
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case R_ARM_ABS32:
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/* Add the addend stored at opaddr to opval */
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opval += *((uint32_t *)opaddr);
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/* Update the absolute address of a load/store instruction */
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*((uint32_t *)opaddr) = (uint32_t)opval;
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case R_ARM_TARGET1:
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*(uint32_t *)loc += sym_base_addr;
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break;
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case R_ARM_PC24:
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case R_ARM_CALL:
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case R_ARM_JUMP24:
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ret = jumps_handler(reloc_type, loc, sym_base_addr, sym_name);
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break;
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case R_ARM_V4BX:
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/* keep Rm and condition bits */
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*(uint32_t *)loc &= OPCODE2ARMMEM(MASK_V4BX_RM_COND);
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/* remove the rest */
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*(uint32_t *)loc |= OPCODE2ARMMEM(MASK_V4BX_NOT_RM_COND);
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break;
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case R_ARM_PREL31:
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ret = prel31_handler(reloc_type, loc, sym_base_addr, sym_name);
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break;
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case R_ARM_REL32:
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*(uint32_t *)loc += sym_base_addr - loc;
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break;
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case R_ARM_MOVW_ABS_NC:
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case R_ARM_MOVT_ABS:
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case R_ARM_MOVW_PREL_NC:
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case R_ARM_MOVT_PREL:
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movs_handler(reloc_type, loc, sym_base_addr, sym_name);
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break;
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case R_ARM_THM_CALL:
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/* Decode the initial addend */
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int32_t addend = arm_bl_blx_decode_addend(opaddr);
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/* Calculate and add the branch offset (addend) */
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addend += ((int32_t)opval) - ((int32_t)opaddr);
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/* Encode the addend */
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arm_bl_blx_encode_addend(opaddr, addend);
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case R_ARM_THM_JUMP24:
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ret = thm_jumps_handler(reloc_type, loc, sym_base_addr, sym_name);
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break;
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case R_ARM_THM_MOVW_ABS_NC:
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case R_ARM_THM_MOVT_ABS:
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case R_ARM_THM_MOVW_PREL_NC:
|
||||
case R_ARM_THM_MOVT_PREL:
|
||||
thm_movs_handler(reloc_type, loc, sym_base_addr, sym_name);
|
||||
break;
|
||||
|
||||
case R_ARM_RELATIVE:
|
||||
*(uint32_t *)loc += load_bias;
|
||||
break;
|
||||
|
||||
case R_ARM_GLOB_DAT:
|
||||
case R_ARM_JUMP_SLOT:
|
||||
*(uint32_t *)loc = sym_base_addr;
|
||||
break;
|
||||
|
||||
default:
|
||||
LOG_DBG("Unsupported ARM elf relocation type %d at address %lx",
|
||||
reloc_type, opaddr);
|
||||
break;
|
||||
LOG_ERR("unknown relocation: %u\n", reloc_type);
|
||||
ret = -ENOEXEC;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Intel Corporation
|
||||
* Copyright (c) 2024 Schneider Electric
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -370,10 +371,29 @@ struct elf64_rela {
|
|||
#define R_ARM_PC24 1
|
||||
#define R_ARM_ABS32 2
|
||||
#define R_ARM_REL32 3
|
||||
#define R_ARM_COPY 4
|
||||
#define R_ARM_THM_CALL 10
|
||||
#define R_ARM_COPY 20
|
||||
#define R_ARM_GLOB_DAT 21
|
||||
#define R_ARM_JUMP_SLOT 22
|
||||
#define R_ARM_RELATIVE 23
|
||||
#define R_ARM_CALL 28
|
||||
#define R_ARM_JUMP24 29
|
||||
#define R_ARM_TARGET1 38
|
||||
#define R_ARM_V4BX 40
|
||||
#define R_ARM_PREL31 42
|
||||
#define R_ARM_MOVW_ABS_NC 43
|
||||
#define R_ARM_MOVT_ABS 44
|
||||
#define R_ARM_MOVW_PREL_NC 45
|
||||
#define R_ARM_MOVT_PREL 46
|
||||
#define R_ARM_ALU_PC_G0_NC 57
|
||||
#define R_ARM_ALU_PC_G1_NC 59
|
||||
#define R_ARM_LDR_PC_G2 63
|
||||
|
||||
#define R_ARM_THM_CALL 10
|
||||
#define R_ARM_THM_JUMP24 30
|
||||
#define R_ARM_THM_MOVW_ABS_NC 47
|
||||
#define R_ARM_THM_MOVT_ABS 48
|
||||
#define R_ARM_THM_MOVW_PREL_NC 49
|
||||
#define R_ARM_THM_MOVT_PREL 50
|
||||
|
||||
#define R_XTENSA_NONE 0
|
||||
#define R_XTENSA_32 1
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Intel Corporation
|
||||
* Copyright (c) 2024 Schneider Electric
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -202,11 +203,15 @@ int llext_add_domain(struct llext *ext, struct k_mem_domain *domain);
|
|||
* or object.
|
||||
*
|
||||
* @param[in] rel Relocation data provided by elf
|
||||
* @param[in] opaddr Address of operation to rewrite with relocation
|
||||
* @param[in] opval Value of looked up symbol to relocate
|
||||
* @param[in] loc Address of operation to rewrite with relocation
|
||||
* @param[in] sym_base_addr Symbol address
|
||||
* @param[in] sym_name Symbol name
|
||||
* @param[in] load_bias .text load address
|
||||
* @retval 0 success
|
||||
* @retval -ENOEXEC invalid relocation
|
||||
*/
|
||||
void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval);
|
||||
|
||||
int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc,
|
||||
uintptr_t sym_base_addr, const char *sym_name, uintptr_t load_bias);
|
||||
/**
|
||||
* @brief Find an ELF section
|
||||
*
|
||||
|
|
|
|||
|
|
@ -714,8 +714,10 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext,
|
|||
}
|
||||
}
|
||||
|
||||
__weak void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval)
|
||||
__weak int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc,
|
||||
uintptr_t sym_base_addr, const char *sym_name, uintptr_t load_bias)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local)
|
||||
|
|
@ -773,6 +775,9 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local
|
|||
if (tgt)
|
||||
llext_link_plt(ldr, ext, &shdr, do_local, tgt);
|
||||
continue;
|
||||
} else if (strcmp(name, ".rel.dyn") == 0) {
|
||||
/* we assume that first load segment starts at MEM_TEXT */
|
||||
loc = (uintptr_t)ext->mem[LLEXT_MEM_TEXT];
|
||||
}
|
||||
|
||||
LOG_DBG("relocation section %s (%d) linked to section %d has %zd relocations",
|
||||
|
|
@ -815,8 +820,11 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local
|
|||
|
||||
op_loc = loc + rel.r_offset;
|
||||
|
||||
/* If symbol is undefined, then we need to look it up */
|
||||
if (sym.st_shndx == SHN_UNDEF) {
|
||||
if (ELF_R_SYM(rel.r_info) == 0) {
|
||||
/* no symbol ex: R_ARM_V4BX relocation, R_ARM_RELATIVE */
|
||||
link_addr = 0;
|
||||
} else if (sym.st_shndx == SHN_UNDEF) {
|
||||
/* If symbol is undefined, then we need to look it up */
|
||||
link_addr = (uintptr_t)llext_find_sym(NULL, name);
|
||||
|
||||
if (link_addr == 0) {
|
||||
|
|
@ -824,6 +832,8 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local
|
|||
"symbol table %s, offset %zd, link section %d",
|
||||
name, (size_t)rel.r_offset, shdr.sh_link);
|
||||
return -ENODATA;
|
||||
} else {
|
||||
LOG_INF("found symbol %s at 0x%lx", name, link_addr);
|
||||
}
|
||||
} else if (ELF_ST_TYPE(sym.st_info) == STT_SECTION ||
|
||||
ELF_ST_TYPE(sym.st_info) == STT_FUNC ||
|
||||
|
|
@ -839,18 +849,17 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local
|
|||
continue;
|
||||
}
|
||||
|
||||
LOG_INF("relocating (linking) symbol %s type %d binding %d ndx %d offset "
|
||||
"%zd link section %d",
|
||||
name, ELF_ST_TYPE(sym.st_info), ELF_ST_BIND(sym.st_info),
|
||||
sym.st_shndx, (size_t)rel.r_offset, shdr.sh_link);
|
||||
|
||||
LOG_INF("writing relocation symbol %s type %zd sym %zd at addr 0x%lx "
|
||||
"addr 0x%lx",
|
||||
name, (size_t)ELF_R_TYPE(rel.r_info), (size_t)ELF_R_SYM(rel.r_info),
|
||||
op_loc, link_addr);
|
||||
|
||||
/* relocation */
|
||||
arch_elf_relocate(&rel, op_loc, link_addr);
|
||||
ret = arch_elf_relocate(&rel, op_loc, link_addr, name,
|
||||
(uintptr_t)ext->mem[LLEXT_MEM_TEXT]);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue