Commit graph

41176 commits

Author SHA1 Message Date
Marcin Niestroj
59648bd1a5 sensors: lis2dh: fix raw value scaling
All values were scaled by 8 instead of 12 for 16g compile-time selected
range. This resulted with values around 6.5 m/s^2. Scaling for runtime
configurable ranges was broken for all except 2g range option due to
totally broken lis2dh_range_to_reg_val().

Fix wrong scaling for 16g compile-time and all runtime selectable ranges
by reworking code that scales raw value. While doing this, change
lis2dh->scale type from 16 to 32 bits. This allows to slightly increase
final result precision by using the fact that raw values have maximum 12
bits precision, allowing us to multiply lis2dh->scale by (1 << 4)
compared to previous implementation.

Fix bug #19872.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-11-13 14:43:25 -06:00
Marcin Niestroj
27b2914da2 sensors: lis2dh: fix raw value to sensor_value conversion
According to struct sensor_value documentation, val2 should be negative
for negative result. So drop code that tries to make val2 positive.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-11-13 14:43:25 -06:00
Andrzej Puzdrowski
aae2c84619 setting: fix NVS error handling on write
In settings write NVS errors were not handled
in a few places.
This patch improve that.

fixes #20515

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2019-11-13 14:11:23 -06:00
David B. Kinder
331214704c doc: New developer getting started guide
As presented to the TSC, Zephyr's out-of-box experience for new
developers is, well, complicated.  A number of suggestions were
presented including simplifying the getting started material to present
a straight-forward path through the setup and installation steps through
to getting a sample application built, flashed, and running.

This PR is a work-in-progress towards addressing this OOB experience
with a minimal-distractions version of the GSG. Alternatives, warnings,
and material that could lead the developer astray were moved to
alternative/advanced instruction documents (based on the previous
separate Linux/macOS/Windows setup guides) and a new "Beyond the GSG"
document.

We do take advantage of a sphinx-tabs extension for synchronized tabs to
present OS-specific instructions: clicking on one tab will display all
same-named tabs throughout the doc.

We hope (and will continue evaluating) that this new GSG gets developers
set up quickly and then we can send them along to other documents to
continue learning about Zephyr and trying other sample apps.

Thanks for all your previous feedback that I've worked
into this new version.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-11-13 14:05:47 -06:00
Wayne Ren
b4ddc10b42 soc: arc: enable SYSTEM_CLOCK_SLOPPY for SMP
in SMP, arc uses gfrc as wall clock, so it's ok
to enable SYSTEM_CLOCK_SLOPPY to avoid unnecessary
interrupts

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-11-13 12:04:18 -08:00
Wayne Ren
66856e5478 drivers: timer: fix the bug for SMP
* fix the smp timer dirver bugs found in debug and test.
for smp case, GFRC is used as clock source, and local
internal timer is used to trigger time event.

* because 64-bits gfrc is used, so idle can be igored as no kernel
tick will be missed

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-11-13 12:04:18 -08:00
Wayne Ren
1e80f25cd1 arch: arc: clear ici interrupt during init
clear the ici interrupts during init

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-11-13 12:04:18 -08:00
Wayne Ren
2b3c9905fe boards: nsim: add missed -firq for nsim_hs_smp
nsim_hs_smp has 2 reg banks, so it should have firq

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-11-13 12:04:18 -08:00
Wayne Ren
d56a12d955 arch: arc: do not use sleep instruction for nsim smp
It's found that in nsim_hs_smp, sometimes the cpu
doesn't response inter-core interrupt after executing sleep
instruction.

It may be a bug of nsim, but needs more time to
investigate the root of this issue.

This commit is a workround for this, as nsim is just an
instruction simulator, no direct impact.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-11-13 12:04:18 -08:00
Wayne Ren
63d3828fa3 arch: arc: split codes for SMP and codes for multicore
reported by #19599, this commit splits the codes for Zephyr SMP
and codes for ARC mulicore.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-11-13 12:04:18 -08:00
Wayne Ren
efc00b5612 arch: arc: necessary fixes after normal idle is used for SMP
* necessary fixes after commit 11bd67db where ipi interrupt is used
to notify other cores to do a thread switch if necessary

* then for arc, it's needed to ignore swap_ok and check whether thread
switch is needed in the exit of irq handling.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-11-13 12:04:18 -08:00
Maureen Helm
1e077ff99d boards: rv32m1_vega: Configure led pinmuxes as gpios
Explicitly configures the rgb led pinmuxes as gpios. Currently the gpio
driver quietly changes the pinmux to gpio mode when configuring a gpio
pin, but this behavior is about to change.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-11-13 12:05:48 -06:00
Peter Bigot
bbcea6fbe6 boards: mark gpio as supported capability where known missing
Some board description files failed to note where gpio was supported,
causing tests to be inappropriately filtered.  Add the feature where
the gpio_basic_api test would use it.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-11-13 12:05:48 -06:00
Christian Taedcke
6486c429f1 dts: silabs: Define all available gpio ports for efr32mg12p
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2019-11-13 12:05:48 -06:00
Christian Taedcke
5ddc46e477 gpio: silabs gecko: Add support for more ports
The gecko gpio driver can now utilize ports a to k.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2019-11-13 12:05:48 -06:00
Christian Taedcke
0ae98c1caf gpio: silabs gecko: Use macro for port initialization
This removes a lot of copy-and-paste.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
38e8bd8444 soc: define gpio pull-down for LPC54114
Add define that maps to IOCON register PULL-DOWN bit.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
20700f912e soc: LPC55xxx clock comment fix
SoC initialization had an incorrect comment regarding system clock.
Corrected from 48Mhz -> 96Mhz.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
de514bc98a soc: enable PINT device at LPC SoC boot
PINT device is enabled when SoC is booting up. Applies to LPC54xxx and
LPC55xxx families.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
f7e2d8a5d6 boards: lpcxpresso55s69 pinmux macros refactor
Board is refactored to use DTS generated value, not use
magic numbers.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
a0f011b2fb dts: lpc devices allocate all gpio interrupts
Allocate all 8 PINT interrupts to ports 0 and 1, allocate 4 to each.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
2e27363e67 dts: NXP LPC gpio updates
NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Stanislav Poboril
aef4541475 dts: nxp_imx6sx_m4: fix gpio5 int num
Fix interrupt number for gpio5

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2019-11-13 12:05:48 -06:00
Marcin Niestroj
dfda0cb114 gpio: stm32: support disabling and reenabling interrupts on gpio pin
Up to now interrupts could be only configured once, with no way to
disable them in runtime.

Allow interrupts to be disabled in runtime and then properly reenabled
on user request. This allows to ignore interrupts when software is not
expecting them.

The improvement over previously reverted patch [1] is that we disable
interrupts only when we configure port for which interrupt line was
previously selected. This for example prevents to disable interrupts
line 2 in case PA2 was previously configured as interrupt source, but we
are currently configuring PB2 as output.

[1] 0951ce2d34 ("gpio: stm32: support disabling and reenabling
  interrupts on pin")

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-11-13 12:05:48 -06:00
Marcin Niestroj
7edcbedc70 gpio: stm32: split helper functions from gpio_stm32_enable_int()
This patch doesn't change functionality, but is only related to improved
readability and reusability.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-11-13 12:05:48 -06:00
Marcin Niestroj
09a57a5e81 gpio: stm32: statify gpio_stm32_enable_int()
This allows compiler to inline function body and reduce overall code
size.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-11-13 12:05:48 -06:00
Erwan Gouriou
dd0d567e8b drivers/gpio: stm32: Rework configure function exit for dual core
With dual core handling introduction, we now need to take care to
always release lock before exiting function.
Rework gpio_stm32_config to take this into account.
Additionally, since ENOSYS usage is resevred to system calls
handling, replace with EIO.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-11-13 12:05:48 -06:00
Piotr Mienkowski
62efdefc7e CODEOWNERS: Add entry for gpio drivers
Adding code owners of gpio drivers.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-11-13 12:05:48 -06:00
Bartosz Sokolski
ecb09931df manifest: update manifest for hal_nordic
Update Zephyr manifest so it picks the tip of hal_nordic.

Signed-off-by: Bartosz Sokolski <bartosz.sokolski@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Bartosz Sokolski
9c54f1f120 tests: drivers: add support for nrf52833 and pca10100
add support for nrf52833 and pca10100

Signed-off-by: Bartosz Sokolski <bartosz.sokolski@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Emil Obalski
446d98b09e bluetooth: Add bluetooth support for nRF52833
This commit adds support for bluetooth in nRF52833 SoC.
Bluetooth radio related files created and added to Zephyr.

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Emil Obalski
11849257c0 boards: Update defconfigs after renaming to USB_NRFX
Name convention for nordic USB driver changed
Kconfig files for custom boards have to be udapted accordingly.
Changes affect only name convention change.

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Emil Obalski
6c82c80a3c drivers: Add support for nRF52833 in several drivers
By adding new SoC to Zephyr drivers has to be updated.
Commit affects:
 - USB driver
	- support for nRF52833 added.
	- support for USB_DEVICE_REMOTE_WAKEUP in hid-mouse added.
 - SPI
 - IEEE 802.15.4
 - CLOCK CONTROL

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Emil Obalski
82c6d7c415 boards: nordic: Add support for nRF52833_pca10100 board
This commit adds support for nRF52833 development board.
Changes afffects:
 - Introduce files related to board description.
 - Add blank documentation file (for future update).
 - configuration files for build process.

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Emil Obalski
3747fd0a68 soc: nordic: Add support for nRF52833
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
 - architecuture files (dtsi)
 - configuration of nrfx drivers
 - adaptation of inclusions based on chosen SoC
 - configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-13 10:33:38 -06:00
Daniel Leung
5c711bd4ba sdk: add support for Zephyr SDK 0.11
This adds support for Zephyr SDK 0.11.* is based on the 0.10 support
with the following changes:

Handle how xtensa toolchains for given targets are organized in SDK
0.11.x.  They have their own directories per specific xtensa SoC.

The x86_64 toolchain in the SDK has been updated to build for 32-bit
targets (as it has 32-bit soft float libraries).  Use this toolchain for
all x86 builds.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-11-13 10:32:02 -06:00
Francois Ramu
02ff0e45a2 boards: arm: st_stm32: add lptimer to nucleo_wb55rg board
This patch introduces the support of the LowPower Timer
     for the STM32WBxx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-11-13 10:31:06 -06:00
Francois Ramu
91884302bf soc: arm: st_stm32: add driver lptimer management to stm32wb series
This patch introduces the support of the Low Power Timer
     for the STM32WBxx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-11-13 10:31:06 -06:00
Francois Ramu
80d58e7f39 driver: timer: st_stm32: add lptimer management to stm32wb series
This patch introduces the support of the LowPower Timer
     for the STM32WBxx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-11-13 10:31:06 -06:00
Alexander Wachter
2302d2615b boards: olimexino_stm32: Enable CAN support for this board
This commit enables CAN support for the Olimexino STM32 board.

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2019-11-13 10:30:19 -06:00
Alexander Wachter
c180e059bf soc: stm32f103Xb: Enable CAN support for this SoC
This commit enables CAN on the STM32F103Xb SoC series.

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2019-11-13 10:30:19 -06:00
Peter A. Bigot
4107bdd264 dts: improve documentation for arduino-header-r3
Provide a clear description of the how the binding maps nexus parent
pin indexes to header pin locations.  Also use the standard name "Uno"
when identifying the header physical layout, contrasted with Mega/Due
which is a different physical layout.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2019-11-13 09:12:14 -06:00
Stephanos Ioannidis
e1827c04d3 sanitycheck: Relocate QEMU-specific code to QEMUHandler.
This commit relocates the QEMU-specific code that currently resides in
ProjectBuilder.run to QEMUHandler.handle, in order to align with what
other handlers are doing.

For more details, refer to the PR #20573.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-13 06:32:31 -06:00
Stephanos Ioannidis
938890041a sanitycheck: Fix incorrect QEMUHandler status reporting.
The current QEMUHandler implementation in sanitycheck does not check
for the process exit code and reports "PASS" even when either the QEMU
executable cannot be launched or exited immediately due to an error
(e.g. unsupported machine type, missing file, ...).

This commit adds QEMU process exit code check and error reporting when
the exit code is a non-zero value.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-13 06:32:31 -06:00
Daniel Leung
fadeb3eb47 soc: intel_s1000_crb: update LP_SRAM macros
The DT_LP_SRAM_* are aliases to DT_MIMO_SRAM_1_* which
are deprecated, so changing these to DT_INST_1_MMIO_SRAM_*.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
eb11e6990b arch: xtensa: use asm for _xt_set_intset/_xt_set_intclear
Use assembly for _xt_set_intset() and _xt_set_intclear() instead of
calling into the Xtensa HAL, allowing these to be inlined.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
7cb9286895 samples: intel_s1000_crb: set CONFIG_NEWLIB_LIBC for math.h
Including math.h requires Newlib so enable it in project
configuration file.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
eca4d69f02 samples: intel_s1000_crb: fix no return on non-void func error
There are compiler error about the entry functions of two threads
not returning anything. So add return statement to fix it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
fc42c82cb9 soc: intel_s1000: define default MEMCTL reg value
When not using XCC, XCHAL_CACHE_MEMCTL_DEFAULT is not defined
which results in some variables not being able to be defined.
So define them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
66aefdbb93 samples: intel_s1000/i2s: fix uninitialized use warning
One of the return variable is declared and used, but never
assigned values. So fix it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00