Add devicetree node of stm32 PWR peripheral that controlls wake-up pins.
The new node includes child nodes for wake-up pins configuration.
We only add these nodes for STM32 SoC series that support Poweroff.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
- The MK22FN512VLH12 chip, installed on frdm_k22f,
has 512 KB of Program Flash and 128KB SRAM
according to the K22P121M120SF7RM.pdf manual (page 55).
- Fix the flash size to 512KB (was 1MB).
- Add nxp_k22fn512.dtsi with correct flash size value.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add a digi_dietemp node for the STM32 Digital Temperature Sensor into
stm32h723.dtsi (used as a base for H723, H725, H730 and H735) and
stm32h7a3.dtsi (used as a base for H7A3, H7B0 and H7B3).
The sensor is not available on other H7 SoCs.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit adds support for the SPI which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes
Signed-off-by: Hao Luo <hluo@ambiq.com>
Align interrupt numbering with RM0436 for STM32MP157.
This will allow EXTI interrupt for line 6, 7, 8, 9, 10 and 11.
Fixes: ff231fa20a ("dts: stm32: Populate new properties for exti nodes")
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Included the nxp_ke1xz.dtsi file to use the same peripheral info,
and overwrite it for different peripherals
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Add DMA channels at SOC level for the LPC55S6x series SOCs, as the dma
requests are SOC specific properties and do not need to be modified at
the board level. Remove any DMA request definitions present at the board
level for the LPC55S69 evaluation board.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit should deal with optimizing device's
operation in terms of power consumption. In this
context:
1. Power and rail managers are enabled so that the
device can enter the sleep state and power
rails be set to the min. required levels.
2. Peripheral blocks should be enabled only when
there is need to do so.
3. Define the internal RCX oscillator as default
low power clock. RC32K should not be used as
it drifts significantly due to temperature and
voltage variations. Thus, affecting the whole
system stability regardless of its calibration.
4. PLL should be enabled only when requested and
on board level LP clock should be switched to
XTAL32K to avoid overhead due to RCX calibration.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
MAX32xxx
MAX32655
MAX32655EVKIT
MAX32655FTHR
MAX32666
MAX32666FTHR
MAX32666FTHR2
MAX32690
MAX32690EVKIT
MAX78xxx
MAX78000
MAX78002
...
When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.
If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.
To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n
MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.
Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
This commit defines the bt-hci subnode under the bleif node on
Ambiq Apollo3 Blue and Apollo3 Blue Plus SOC.
Also add the default configurations for Bluetooth feature on Ambiq
apollo3_evb and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commits add the BLEIF instance which is compatible with
"ambiq,spi-bleif" on Ambiq apollo3p_evb and apollo3_evb.
Also creates the default pinctrl for the defined instance.
Signed-off-by: Aaron Ye <aye@ambiq.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit adds support for the I2C which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes
Signed-off-by: Hao Luo <hluo@ambiq.com>
The RTXXX and RW61X DT are using syscon compatible
depsite not having a syscon. This is a technical debt
to remain aware of. The reason they use these compatibles
is to use the syscon driver which is a shim to an SDK API
that is somewhat similar to syscon.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Fix mcxn94x flash write-block-size from 16 to 128.
- Fix flash_program() return error 0x65,
that means "Address or length does not meet the required alignment."
- The mcxn94x Flash ROM API flash_program() start address and
the length must be 128 bytes-aligned.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
port infineon CAT1A (psoc6) to HWMv2:
1. move dts\arm\cypress\** to dts\arm\infineon\cat1a\legacy
2. remove dts\arm\cypress\**
3. rename dts\arm\infineon\psoc6 to dts\arm\infineon\cat1a
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Although we can get the number of configured OUT and IN endpoints and
endpoint capabilities from the DWC GHWCFGn registers, we need to
configure the number of endpoint configuration structs at build time. On
some platforms, we cannot access the hardware register at pre-init, so
we use the GHWCFGn values from the devicetree to provide endpoint
capabilities. This can be considered a workaround, and we may change the
upper layer internals to avoid it in the future.
Also, add a new vendor quirk to fill in platform-specific controller
capabilities.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add the Kconfig options and use the aliased
addresses for the bootcode regions of the IMX7D
and IMX6SX SOCs to allow the Linux rproc
framework to load the irq-vectors into
the correct memory areas.
Activating this option might enlarge the bin
file if the zephyr,flash and rom_start chosen
region addresses are not matching.
It is up to the user to enable this feature
based on code location choices (OCRAM, DDR, TCM...).
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
By default, the QSPI region is marked as EXTMEM and inaccessible
(see #57467), mark the first 64MB as IO on stm32f769i_disco.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Define the xspi node instead of ospi. Note that RCC CCIPR4 register
keeps the OCTOSP1 for clock domain selection.
Change the header file to xspi for the stm32 devices with xspi
peripheral. Keep the flash_controller/ospi.h for bindings compatibilty.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add USDHC0 node to the mcxn94x devicetree. This node describes the one
instance of the Ultra Secured Digital Host Controller IP present on the
MCXN94x series SOCs.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add DT node entries to RW for DAC and ADC.
Support the SOC required initialization of the DAC and ADC on RW.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commits adds required pinctrl node to provide the corresponding SIO
clock selection for the Serial Port under the different VOSCCLK.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
iMXRT1042 SOC should be clocked at 528 MHz maximum. Correct the clock
setup to use the system PLL.
Fixes#70755
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of the system pll on the iMXRT10xx series parts, via
a fractional pll node under the CCM module.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
UART2 and UART3 (unlink UART) do support hardware flow control.
This simply add necessary flag that is already handled in the code.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Correction of the reg address of enet2 for nxp_rt1060.
Regression introduced at 537d5c310c
Signed-off-by: Matthias Alleman <matthias.alleman@basalte.be>
This commit adds flash controller instance for Ambiq Apollo3 Blue SOC
and Apollo3 Blue Plus SOC.
Also create the partitions on this flash controller node for apollo3_evb
and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
In the <board>.dts file, the definition for usart0 was found to be
redundant as the same information is already provided in the included
.dtsi file. this commit removes the duplicate definition of usart0,
resulting in a cleaner and more maintainable device tree configuration.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
Add mdio node for h5 and h7 series.
Since MDIO registers are part of the same ETH hw IP, keeping mdio
node just as a child of mac/eth, cannot see as appropriate to assign
an adddress to it.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Set RNG address to its non-secure alias.
See RM0493 STM32WBA5 Reference manual for details.
Using the secure alias (0x5..)instead of the non-secure alias (0x4..)
for this peripheral results in a SecureFault during kernel init if
TrustZone is activated, Zephyr is running as NSPE and RNG is
enabled.
Signed-off-by: Louis Feller <louis.feller@st.com>
Commit 246ea739bb ("dts/arm/st: wl: increase Sub-GHz SPI frequency to
12MHz") increased the Sub-GHz to 12 MHz. This matches the SX126x
datasheet, but there is no information about the maximum speed in the
STM32WL datasheet or reference.
This works fine when not using DMA. However with DMA activated (adding
entries to the device-tree and enabling CONFIG_SPI_STM32_DMA), I have
encountered some rare corruption. When it happens, the read from the
Sub-GHz device gets an extra 0x00 byte prepended, which confuses the
LoRaMac-node library and causes reception failures. Decreasing the
frequency to the next round number, that is 8 MHz (i.e. increasing the
prescaler from 4 to 6) fixes all the issues I encountered.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
1) Replace master/slave in API for new terms in eSPI spec 1.5
2) Reflect eSPI VW change and macro changes across eSPI drivers
3) Update terms in eSPI driver sample and eSPI test driver
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Update m2l31x.dtsi for adc support and update adc_numaker.c
to support acquisition time in 0~255 ADC ticks.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This commit implement the UART asynchronous API mode support.
When the API is used, the UART hardware cooperates with the DMA (MDMA)
module to handle the the data transfer and receiving.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Squash the two copies of this file found in `dts/arm` and `dts/arm64`.
Their contents were identical up to devicetree property ordering.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This file was moved to the `dts/arm64` directory 3 years ago:
3539c2fbb3
However, the original file in `dts/arm` was left by mistake. Since then,
it's been unused and seldom updated, but it hasn't diverged much.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This file is basically a copy of the AM62x M4 dtsi but an
additional mcu_uart1 interface.
The internal clock frequency feeded into the UART IP is
96 MHz instead of 48 MHz, which is different to the AM62x.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
We define two frequencies in the am62x_m4.dtsi file.
Use DT_FREQ_M for both frequency to make them more
human-readable and easier to understand.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Updated dts for MCXN94x with support for CTimer.
Signed-off-by: William Tang <william.tang@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
FTM internal counter can be clocked by one of three clock sources
independent of the module bus clock. This patch introduces a DT property
to perform the clock selection from DT.
DT sources are updated to keep the current clock selection for all boards,
with exception of ucans32k1sic board which is migrated to use system
clock by default, as this seems to be a better choice for most cases.
Some PWM LED samples require slower clock so overlays are added for
those cases.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Set RTC clock source to the internal 32 KHz LPO. Currently RTC clock is
used to source RTC counter and FTM counter.
Fixes#71289
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert all of the NXP SOCs with ENET to use the new
binding scheme, which is used by the new driver.
Convert any boards using this SOC to the new scheme as well,
and remove from the documentation the bit about the experimental
nature of the new driver and the overlay that shall no longer exist.
Some of the boards I do not have the hardware of, so apologies
if something breaks, as I have no way to know. All the boards
were made sure to at least build.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
