This commit should deal with updating
the way USBD was handling the DMA
engine. Based on the #73803 request
DMA should be handled via the DMA
driver API class and not directly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Cleanup leading spaces found via the following regexes:
r" compatible ="
r"^ "
in:
zephyr/**/*.dts
zephyr/**/*.dtsi
Signed-off-by: Jordan Yates <jordan@embeint.com>
Apply the workaround for the issue "BBRAM First Byte" in the
NPCX49nF_Errata. This bypass limits the access to the BBRAMs' first byte
(i.e., the offset 0). As a result, only 127 bytes are available in npcx4
chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Clock NXP_S32_FTMx_CLK reference the output of PCC_FTMx clocks, but
FTM has an internal clock mux to select the clock source of the
counter, which for ucans32k1sic board is set to system clock. Fix the
clock nodes to use the correct clock name. So far this was working
because both NXP_S32_FTMx_CLK and NXP_S32_CORE_CLK are configured to
the same frequency.
Fixes#74348
Signed-off-by: Manuel Argüelles <marguelles.dev@gmail.com>
The current atmel,sam-tc-qdec sensor implementation shared the timer
counter node. This create issues when users wants define both modes.
The current proposal changes the qdec dedinition to be a child of
tc and refactor all the chain of definitions.
Fixes#71312
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
After changing the VEVIF and BELLBOARD names,
the dts for the individual boards must be aligned.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Nordic devices are commonly used with the nRF Connect SDK.
There the SoftDevice Controller is set as the default
Bluetooth Controller. To avoid confusion when reading DTS
and Kconfig files, clarify this by adding a note.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Add the IWDG and WWDG watchdog peripherals
the ADC1 & 2 peripherals with sensor for die temperature and voltage
the RNG entropy generator
Signed-off-by: Francois Ramu <francois.ramu@st.com>
LPC GPIO binding was wrong in that the reg address
on the simple soc bus was given as an index of the gpio ports
within a gpio controller. Fix this by putting the GPIO node
on the simple bus as a single node with the correct base address,
and make the ports children of this node.
Change the driver to get the port number from the reg address
instead of a custom property, and get base address from DT instead
of the SDK macro definition.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
define usbphy in DT and controller DT node ref to usbphy node.
define the usbphy yaml and update ehci and ip3511 yaml for usbphy.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
I also added an overlay file for the nucleo_h563zi board to the
samples/boards/stm32/backup_sram example.
Signed-off-by: Thorsten Spätling <thorsten.spaetling@vierling.de>
Convert the slz_hci.c HCI driver to use the new HCI driver API. This also
fixes the HCI bus type to correctly indicate VIRTUAL instead of UART.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Convert the hci_nxp.c HCI driver to use the new HCI driver API. Also move
the driver binding under dts/bindings/bluetooth, like all other HCI driver
bindings.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Convert the hci_stm32wba.c driver to the new HCI API. Unlike in most cases,
the devicetree node is already enabled on the SoC level (rather than board
level). This is in order to mirror how the Kconfig option was originally
enabled, i.e. on the SoC level.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Update the native controller to the new HCI driver API. The devicetree
node is placed under existing `radio` nodes, which seemed like the most
intuitive option.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Added a single instance lptmr node on the
mcxn947 soc dts. Updated counter lptmr to
have max value property.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
This driver can be used for both mcux and
s32k series SoCs which have flexio IP.
PWM channel is automatically allocated by
flexio driver based on the available timers.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Fix simple bus reg / ranges warning from GPIO
nodes by giving the parent nodes addresses
and describing a ranges other than empty.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
On STM32G0, the backup memory is defined as part of the TAMP peripheral.
Use the same workaround as on STM32WL to add the node as part of the
RTC.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Adds channel 15 to the pool of grtc channels available
for allocation (i.e. with 'z_nrf_grtc_timer_chan_alloc')
on nRF54H20.
The change is motivated by lack of available channels
for the nrf_802154_timestamper when building for nRF54H20.
Signed-off-by: Piotr Koziar <piotr.koziar@nordicsemi.no>
This commit should address the #73803 issue
where the DMA node does not provide support
for the #dma-cells binding. Peripherals should
specify one or more DMA channels via the dmas
and optionally dma-names DT properties.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Support NXP ENET_1G on mimxrt1170_evk/mimxrt1176/cm7 platform.
Added test configuration sample.net.zperf.nxp_enet1g and
documented the usage of the ethernet driver with ENET_1G
peripheral.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add devicetree nodes for the two FlexCAN instances present on the
MCXN94x. Only CAN classic is enabled for now due to issues with FlexCAN FD
in relation to the implementation on this SoC.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add the new stm32h7rs serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for configuration of the ARM PLL on the iMXRT1170/1160
series SOCs. This PLL is used to generate the M7 core frequency, and is
an integer pll. Provide default configurations for the RT1160 and RT1170
targeting 600MHz and 1GHz respectively.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
