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zephyr/soc/riscv/riscv-privilege/sifive-freedom/soc.h

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riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
riscv: Rename the FE310 SoC to Sifive Freedom FE310 is the name of one SoC out of a range of products in the SiFive Freedom line. The FE310 SoC port in Zephyr is compatible with all of these products, so rename the SoC to SiFive Freedom Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-15 15:41:21 -07:00
* @file SoC configuration macros for the SiFive Freedom processor
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
*/
riscv: freedom: rename RISCV32 to RISCV This code is common to 32- and 64-bit builds. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-18 23:05:53 -04:00
#ifndef __RISCV_SIFIVE_FREEDOM_SOC_H_
#define __RISCV_SIFIVE_FREEDOM_SOC_H_
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
#include <soc_common.h>
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 18:33:12 +09:00
#if defined(CONFIG_SOC_RISCV_SIFIVE_FREEDOM)
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
/* PINMUX IO Hardware Functions */
riscv: Rename the FE310 SoC to Sifive Freedom FE310 is the name of one SoC out of a range of products in the SiFive Freedom line. The FE310 SoC port in Zephyr is compatible with all of these products, so rename the SoC to SiFive Freedom Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-15 15:41:21 -07:00
#define SIFIVE_PINMUX_IOF0 0x00
#define SIFIVE_PINMUX_IOF1 0x01
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
/* PINMUX MAX PINS */
riscv: Rename the FE310 SoC to Sifive Freedom FE310 is the name of one SoC out of a range of products in the SiFive Freedom line. The FE310 SoC port in Zephyr is compatible with all of these products, so rename the SoC to SiFive Freedom Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-15 15:41:21 -07:00
#define SIFIVE_PINMUX_PINS 32
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
arch: riscv32: fe310: Always-On domain adress definition Added always-on domain address definition Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
2018-04-04 22:11:07 +02:00
/* Clock controller. */
#define PRCI_BASE_ADDR 0x10008000
/* Always ON Domain */
riscv: Rename the FE310 SoC to Sifive Freedom FE310 is the name of one SoC out of a range of products in the SiFive Freedom line. The FE310 SoC port in Zephyr is compatible with all of these products, so rename the SoC to SiFive Freedom Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-15 15:41:21 -07:00
#define SIFIVE_PMUIE 0x10000140
#define SIFIVE_PMUCAUSE 0x10000144
#define SIFIVE_PMUSLEEP 0x10000148
#define SIFIVE_PMUKEY 0x1000014C
#define SIFIVE_SLEEP_KEY_VAL 0x0051F15E
arch: riscv32: fe310: Always-On domain adress definition Added always-on domain address definition Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
2018-04-04 22:11:07 +02:00
riscv: Rename the FE310 SoC to Sifive Freedom FE310 is the name of one SoC out of a range of products in the SiFive Freedom line. The FE310 SoC port in Zephyr is compatible with all of these products, so rename the SoC to SiFive Freedom Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-15 15:41:21 -07:00
#define SIFIVE_BACKUP_REG_BASE 0x10000080
arch: riscv32: fe310: Always-On domain adress definition Added always-on domain address definition Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
2018-04-04 22:11:07 +02:00
soc: riscv: add initial support for SiFive Freedom U740 This patch adds support for SiFive Freedom U740 SoC. First version is minimum only using UART, SPI and L2-LIM area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-08-22 15:54:41 +09:00
#elif defined(CONFIG_SOC_RISCV_SIFIVE_FU540) || defined(CONFIG_SOC_RISCV_SIFIVE_FU740)
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 18:33:12 +09:00
/* Clock controller. */
#define PRCI_BASE_ADDR 0x10000000
boards: riscv: hifive_unleashed: add GPIO support This patch adds GPIO and 96board LS (Low Speed)iexpansion connector support for SiFive HiFive Unleashed and also enables GPIO basic test. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2022-01-19 17:31:21 +09:00
/* PINMUX MAX PINS */
#define SIFIVE_PINMUX_PINS 16
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 18:33:12 +09:00
#endif
/* Timer configuration */
#define RISCV_MTIME_BASE 0x0200BFF8
#define RISCV_MTIMECMP_BASE 0x02004000
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
/* lib-c hooks required RAM defined variables */
devicetree: Remove DT_SRAM_{BASE_ADDRESS,SIZE}, use CONFIG_* versions The SRAM address and size are currently available as both DT_SRAM_{BASE_ADDRESS,SIZE} and as CONFIG_SRAM_{BASE_ADDRESS,SIZE} (via the Kconfig preprocessor). Use the CONFIG_SRAM_* versions everywhere, and remove generation of the DT_SRAM_* versions from gen_defines.py. The Kconfig symbols currently depend on 'ARC || ARM || NIOS2 || X86'. Not sure why, so I removed it. It looks like no configuration files set CONFIG_SRAM_* at the moment, so another option might be to use the DT_* symbols everywhere instead. Some Kconfig.defconfig.series files add defaults to them though. Also improve the help texts for CONFIG_SRAM_* to say that they normally come from devicetree rather than configuration files. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-26 16:08:19 +01:00
#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-14 22:15:59 +01:00
riscv: freedom: rename RISCV32 to RISCV This code is common to 32- and 64-bit builds. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-18 23:05:53 -04:00
#endif /* __RISCV_SIFIVE_FREEDOM_SOC_H_ */
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