feaf0070fc
This patch adds GPIO and 96board LS (Low Speed)iexpansion connector support for SiFive HiFive Unleashed and also enables GPIO basic test. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the SiFive Freedom processor
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*/
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#ifndef __RISCV_SIFIVE_FREEDOM_SOC_H_
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#define __RISCV_SIFIVE_FREEDOM_SOC_H_
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#include <soc_common.h>
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#if defined(CONFIG_SOC_RISCV_SIFIVE_FREEDOM)
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/* PINMUX IO Hardware Functions */
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#define SIFIVE_PINMUX_IOF0 0x00
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#define SIFIVE_PINMUX_IOF1 0x01
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/* PINMUX MAX PINS */
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#define SIFIVE_PINMUX_PINS 32
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/* Clock controller. */
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#define PRCI_BASE_ADDR 0x10008000
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/* Always ON Domain */
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#define SIFIVE_PMUIE 0x10000140
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#define SIFIVE_PMUCAUSE 0x10000144
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#define SIFIVE_PMUSLEEP 0x10000148
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#define SIFIVE_PMUKEY 0x1000014C
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#define SIFIVE_SLEEP_KEY_VAL 0x0051F15E
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#define SIFIVE_BACKUP_REG_BASE 0x10000080
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#elif defined(CONFIG_SOC_RISCV_SIFIVE_FU540) || defined(CONFIG_SOC_RISCV_SIFIVE_FU740)
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/* Clock controller. */
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#define PRCI_BASE_ADDR 0x10000000
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/* PINMUX MAX PINS */
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#define SIFIVE_PINMUX_PINS 16
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#endif
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/* Timer configuration */
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#define RISCV_MTIME_BASE 0x0200BFF8
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#define RISCV_MTIMECMP_BASE 0x02004000
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/* lib-c hooks required RAM defined variables */
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#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
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#endif /* __RISCV_SIFIVE_FREEDOM_SOC_H_ */
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