Commit graph

10 commits

Author SHA1 Message Date
Katsuhiro Suzuki
feaf0070fc boards: riscv: hifive_unleashed: add GPIO support
This patch adds GPIO and 96board LS (Low Speed)iexpansion  connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2022-02-21 20:46:47 -05:00
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Katsuhiro Suzuki
ca853af0b9 soc: riscv: add initial support for SiFive Freedom U740
This patch adds support for SiFive Freedom U740 SoC.
First version is minimum only using UART, SPI and L2-LIM area.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-03 09:52:26 -04:00
Katsuhiro Suzuki
82f75ed337 soc: riscv: add initial support for SiFive Freedom U540
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-03 09:52:26 -04:00
Kumar Gala
f6b7dd09ec pinmux: sifive: Convert SiFive pinmux to be devicetree based
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:33:00 -05:00
Kumar Gala
8e65c69bb4 soc: sifive: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 16:06:09 -05:00
Ulf Magnusson
4e85006ba4 dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}
generated_dts_board.h is pretty redundant and confusing as a name. Call
it devicetree.h instead.

dts.h would be another option, but DTS stands for "devicetree source"
and is the source code format, so it's a bit confusing too.

The replacement was done by grepping for 'generated_dts_board' and
'GENERATED_DTS_BOARD'.

Two build diagram and input-output SVG files were updated as well, along
with misc. documentation.

hal_ti, mcuboot, and ci-tools updates are included too, in the west.yml
update.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-17 17:57:59 +01:00
Ulf Magnusson
def1f0e2d5 devicetree: Remove DT_SRAM_{BASE_ADDRESS,SIZE}, use CONFIG_* versions
The SRAM address and size are currently available as both
DT_SRAM_{BASE_ADDRESS,SIZE} and as CONFIG_SRAM_{BASE_ADDRESS,SIZE} (via
the Kconfig preprocessor).

Use the CONFIG_SRAM_* versions everywhere, and remove generation of the
DT_SRAM_* versions from gen_defines.py.

The Kconfig symbols currently depend on 'ARC || ARM || NIOS2 || X86'.
Not sure why, so I removed it.

It looks like no configuration files set CONFIG_SRAM_* at the moment, so
another option might be to use the DT_* symbols everywhere instead. Some
Kconfig.defconfig.series files add defaults to them though.

Also improve the help texts for CONFIG_SRAM_* to say that they normally
come from devicetree rather than configuration files.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-07 17:19:36 +01:00
Nicolas Pitre
75bf3c5368 riscv: freedom: rename RISCV32 to RISCV
This code is common to 32- and 64-bit builds.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-08 00:29:24 -04:00
Nicolas Pitre
1f4b5ddd0f riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00
Renamed from soc/riscv32/riscv-privilege/sifive-freedom/soc.h (Browse further)