2019-11-04 09:30:05 +01:00
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/*
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* Copyright (c) 2019 STMicroelectronics.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/g4/stm32g474Xe.dtsi>
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2020-10-02 15:28:52 +02:00
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#include <st/g4/stm32g474r(b-c-e)tx-pinctrl.dtsi>
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2019-11-04 09:30:05 +01:00
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#include "arduino_r3_connector.dtsi"
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/ {
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model = "STMicroelectronics STM32G474RE-NUCLEO board";
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2020-09-25 14:57:24 +02:00
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compatible = "st,stm32g474re-nucleo";
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2019-11-04 09:30:05 +01:00
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chosen {
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zephyr,console = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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canbus: rename zephyr,can-primary chosen property to zephyr,canbus
Rename the Zephyr chosen property for specifying the default CAN bus
controller from "zephyr,can-primary" to "zephyr,canbus".
The "zephyr,can-primary" property name was selected in antipation of
adding support for redundant CAN networks, which we have yet to
add. Meanwhile, the "primary" term causes confusion for non-redundant
CAN bus configurations (and the "can" term doesn't match the name of the
Zephyr CAN bus subsystem).
The CAN in Automation (CiA) 302-6, which deals with CANopen network
redundancy, uses the terms "default interface" and "redundant
interface". If/when we add support for redundant CAN networks, the
"zephyr,canbus" chosen property can be supplemented with a
"zephyr,canbus-redundant" chosen property.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-11-02 16:49:04 +01:00
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zephyr,canbus = &can1;
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2019-11-04 09:30:05 +01:00
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};
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leds {
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compatible = "gpio-leds";
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green_led: led_0 {
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2019-10-03 18:30:21 +02:00
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gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
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2019-11-04 09:30:05 +01:00
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label = "User LD2";
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};
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};
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pwmleds {
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compatible = "pwm-leds";
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green_pwm_led: green_pwm_led {
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2022-04-06 10:22:59 +02:00
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pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
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2019-11-04 09:30:05 +01:00
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button: button {
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label = "User";
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2019-10-03 18:30:21 +02:00
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gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
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2019-11-04 09:30:05 +01:00
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};
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};
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aliases {
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led0 = &green_led;
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pwm-led0 = &green_pwm_led;
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sw0 = &user_button;
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2022-07-19 10:33:14 +02:00
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watchdog0 = &iwdg;
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2019-11-04 09:30:05 +01:00
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};
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};
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2022-09-07 09:13:35 +02:00
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&clk_lsi {
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status = "okay";
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};
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2021-04-29 15:11:59 +02:00
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&clk_hse {
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clock-frequency = <DT_FREQ_M(24)>;
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status = "okay";
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};
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&pll {
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div-m = <6>;
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mul-n = <85>;
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div-p = <7>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(170)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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};
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2019-11-04 09:30:05 +01:00
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&usart1 {
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2020-10-06 14:36:06 +02:00
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pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
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2021-09-07 16:38:13 +02:00
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pinctrl-names = "default";
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2019-11-04 09:30:05 +01:00
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current-speed = <115200>;
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status = "okay";
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};
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&lpuart1 {
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2020-10-06 14:36:06 +02:00
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pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
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2021-09-07 16:38:13 +02:00
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pinctrl-names = "default";
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2019-11-04 09:30:05 +01:00
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current-speed = <115200>;
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status = "okay";
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};
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&i2c1 {
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2020-10-12 17:53:50 +02:00
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pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
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2021-11-08 10:59:17 +01:00
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pinctrl-names = "default";
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2019-11-04 09:30:05 +01:00
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status = "okay";
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};
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&spi1 {
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2021-06-10 11:16:09 +02:00
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pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
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2021-11-08 12:23:47 +01:00
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pinctrl-names = "default";
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2021-06-10 11:16:09 +02:00
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cs-gpios = <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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2020-10-15 17:03:11 +02:00
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status = "okay";
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};
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&spi2 {
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pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
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&spi2_miso_pb14 &spi2_mosi_pb15>;
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2021-11-08 12:23:47 +01:00
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pinctrl-names = "default";
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2020-10-15 17:03:11 +02:00
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status = "okay";
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};
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&spi3 {
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/* SPI3 on the ST Morpho Connector CN7 pins 17, 1, 2, 3*/
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pinctrl-0 = <&spi3_nss_pa15 &spi3_sck_pc10
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&spi3_miso_pc11 &spi3_mosi_pc12>;
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2021-11-08 12:23:47 +01:00
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pinctrl-names = "default";
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2019-11-04 09:30:05 +01:00
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status = "okay";
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};
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&timers2 {
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status = "okay";
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2020-05-01 16:13:37 +02:00
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pwm2: pwm {
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2019-11-04 09:30:05 +01:00
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status = "okay";
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2022-03-04 12:28:00 +01:00
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pinctrl-0 = <&tim2_ch1_pa5>;
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2021-11-08 11:48:51 +01:00
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pinctrl-names = "default";
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2021-03-30 17:53:13 +02:00
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};
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};
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&timers3 {
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2021-10-20 19:47:14 +02:00
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st,prescaler = <10000>;
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2021-03-30 17:53:13 +02:00
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status = "okay";
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pwm3: pwm {
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status = "okay";
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pinctrl-0 = <&tim3_ch1_pb4>;
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2021-11-08 11:48:51 +01:00
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pinctrl-names = "default";
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2019-11-04 09:30:05 +01:00
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};
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};
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&rtc {
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2022-09-07 09:13:35 +02:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
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<&rcc STM32_SRC_LSI RTC_SEL(2)>;
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2019-11-04 09:30:05 +01:00
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status = "okay";
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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2022-04-20 12:45:20 +02:00
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/* Set 4Kb of storage at the end of the 128Kb of flash */
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storage_partition: partition@1f000 {
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2019-11-04 09:30:05 +01:00
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label = "storage";
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2022-04-20 12:45:20 +02:00
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reg = <0x0001f000 DT_SIZE_K(4)>;
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2019-11-04 09:30:05 +01:00
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};
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};
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};
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&iwdg {
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status = "okay";
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};
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2020-07-31 12:57:07 +02:00
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&rng {
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status = "okay";
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};
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2020-08-24 11:57:18 +02:00
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&adc1 {
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2020-10-12 08:10:50 +02:00
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pinctrl-0 = <&adc1_in1_pa0>;
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2021-11-05 15:14:51 +01:00
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pinctrl-names = "default";
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2020-08-24 11:57:18 +02:00
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status = "okay";
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};
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2021-02-07 15:50:49 +01:00
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2022-05-17 17:34:30 +02:00
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&die_temp {
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status = "okay";
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};
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2022-03-07 10:37:30 +01:00
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&dac1 {
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pinctrl-0 = <&dac1_out1_pa4>;
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pinctrl-names = "default";
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status = "okay";
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};
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2021-02-07 15:50:49 +01:00
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&can1 {
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2022-09-03 22:01:56 +02:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>,
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<&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
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2021-02-07 15:50:49 +01:00
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pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
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2021-11-05 15:54:29 +01:00
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pinctrl-names = "default";
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2021-02-07 15:50:49 +01:00
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bus-speed = <125000>;
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bus-speed-data = <1000000>;
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status = "okay";
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};
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