boards: nucleo_g474re: Use dts for clocks configuration
Convert board to use of device tree for clocks configuration. Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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2 changed files with 24 additions and 35 deletions
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@ -51,6 +51,29 @@
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};
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};
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&clk_hse {
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clock-frequency = <DT_FREQ_M(24)>;
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status = "okay";
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};
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&pll {
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div-m = <6>;
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mul-n = <85>;
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div-p = <7>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(170)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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};
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&usart1 {
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pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
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current-speed = <115200>;
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@ -3,14 +3,6 @@
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CONFIG_SOC_SERIES_STM32G4X=y
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CONFIG_SOC_STM32G474XX=y
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# 170MHz system clock only in 'boost power' mode.
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# RM0440, section 5.1.5 states that the R1MODE bit
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# must be cleared before system can be 170MHz.
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=170000000
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# 150MHz system clock in 'normal power' mode
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# CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000
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# enable uart driver
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CONFIG_SERIAL=y
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@ -20,35 +12,9 @@ CONFIG_PINMUX=y
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# enable GPIO
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CONFIG_GPIO=y
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# clock configuration
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# Enable Clocks
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CONFIG_CLOCK_CONTROL=y
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# Use PLLCLK for SYSCLK
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# Use HSE (24MHz) to feed into PLL
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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CONFIG_CLOCK_STM32_HSE_CLOCK=24000000
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
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CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
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# Produce 150MHz clock at PLLCLK output
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# CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
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# CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=75
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# Produce 170MHz clock at PLLCLK output
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=6
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=85
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# Produce Max (150MHz or 170MHz) HCLK
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# Produce Max (150MHz or 170MHz) APB1 clocks and APB2 clocks
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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# Console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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