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boards: arm: Add RTC clock source for STM32 boards dts

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For every board using an STM32, add the RTC clock source in its dts

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier 2022-09-07 09:13:35 +02:00 • committed by Fabio Baltieri
commit dbbfff5002
72 changed files with 416 additions and 0 deletions
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6
boards/arm/96b_argonkey/96b_argonkey.dts
View file

@ -47,6 +47,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
@ -161,5 +165,7 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/96b_carbon/96b_carbon.dts
View file

@ -53,6 +53,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
@ -175,5 +179,7 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/96b_neonkey/96b_neonkey.dts
View file

@ -56,6 +56,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -117,5 +121,7 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.dts
View file

@ -51,6 +51,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
@ -205,5 +209,7 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/96b_wistrio/96b_wistrio.dts
View file

@ -55,6 +55,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -120,6 +124,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.dts
View file

@ -35,6 +35,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(12)>;
status = "okay";
@ -98,6 +102,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.dts
View file

@ -71,6 +71,10 @@
cpu-power-states = <&stop>;
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -149,6 +153,8 @@ arduino_i2c: &i2c1 {};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.dts
View file

@ -48,6 +48,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -206,6 +210,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/black_f407ve/black_f407ve.dts
View file

@ -57,6 +57,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -104,6 +108,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/black_f407zg_pro/black_f407zg_pro.dts
View file

@ -56,6 +56,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -103,6 +107,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/blackpill_f401cc/blackpill_f401cc.dts
View file

@ -107,6 +107,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
@ -122,6 +124,10 @@ zephyr_udc0: &usbotg_fs {
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";

6
boards/arm/blackpill_f401ce/blackpill_f401ce.dts
View file

@ -107,6 +107,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
@ -122,6 +124,10 @@ zephyr_udc0: &usbotg_fs {
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";

6
boards/arm/blackpill_f411ce/blackpill_f411ce.dts
View file

@ -108,6 +108,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
@ -123,6 +125,10 @@ zephyr_udc0: &usbotg_fs {
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";

6
boards/arm/disco_l475_iot1/disco_l475_iot1.dts
View file

@ -78,6 +78,10 @@
cpu-power-states = <&stop0 &stop1 &stop2>;
};
&clk_lsi {
status = "okay";
};
&clk_lse {
status = "okay";
};
@ -250,6 +254,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

2
boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts
View file

@ -167,6 +167,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/mikroe_clicker_2/mikroe_clicker_2.dts
View file

@ -52,6 +52,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
@ -96,6 +100,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f031k6/nucleo_f031k6.dts
View file

@ -40,6 +40,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -101,5 +105,7 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f091rc/nucleo_f091rc.dts
View file

@ -60,6 +60,10 @@
status = "okay";
};
&clk_lsi {
status = "okay";
};
&pll {
prediv = <1>;
mul = <6>;
@ -118,6 +122,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f207zg/nucleo_f207zg.dts
View file

@ -76,6 +76,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -138,6 +142,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f302r8/nucleo_f302r8.dts
View file

@ -42,6 +42,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -107,6 +111,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f303k8/nucleo_f303k8.dts
View file

@ -40,6 +40,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -97,5 +101,7 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f303re/nucleo_f303re.dts
View file

@ -43,6 +43,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -79,6 +83,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f334r8/nucleo_f334r8.dts
View file

@ -43,6 +43,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -110,6 +114,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f401re/nucleo_f401re.dts
View file

@ -53,6 +53,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -155,6 +159,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f410rb/nucleo_f410rb.dts
View file

@ -42,6 +42,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -101,6 +105,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f411re/nucleo_f411re.dts
View file

@ -42,6 +42,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -111,5 +115,7 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f412zg/nucleo_f412zg.dts
View file

@ -52,6 +52,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -120,5 +124,7 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f413zh/nucleo_f413zh.dts
View file

@ -52,6 +52,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -120,5 +124,7 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f429zi/nucleo_f429zi.dts
View file

@ -55,6 +55,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -139,6 +143,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f446re/nucleo_f446re.dts
View file

@ -43,6 +43,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -109,6 +113,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f446ze/nucleo_f446ze.dts
View file

@ -53,6 +53,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -158,6 +162,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f746zg/nucleo_f746zg.dts
View file

@ -62,6 +62,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -142,6 +146,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_f767zi/nucleo_f767zi.dts
View file

@ -63,6 +63,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -149,6 +153,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

2
boards/arm/nucleo_g071rb/nucleo_g071rb.dts
View file

@ -99,6 +99,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

2
boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts
View file

@ -106,6 +106,8 @@ zephyr_udc0: &usb {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_g431rb/nucleo_g431rb.dts
View file

@ -52,6 +52,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
@ -128,6 +132,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_g474re/nucleo_g474re.dts
View file

@ -53,6 +53,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
@ -139,6 +143,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_h723zg/nucleo_h723zg.dts
View file

@ -62,6 +62,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -108,6 +112,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_h743zi/nucleo_h743zi.dts
View file

@ -60,6 +60,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -101,6 +105,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts
View file

@ -45,6 +45,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -74,6 +78,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_h753zi/nucleo_h753zi.dts
View file

@ -59,6 +59,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -100,6 +104,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l152re/nucleo_l152re.dts
View file

@ -44,6 +44,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -85,6 +89,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.dts
View file

@ -42,6 +42,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -101,6 +105,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l432kc/nucleo_l432kc.dts
View file

@ -33,6 +33,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -100,6 +104,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.dts
View file

@ -43,6 +43,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -117,6 +121,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l452re/nucleo_l452re_common.dtsi
View file

@ -34,6 +34,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -101,6 +105,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l476rg/nucleo_l476rg.dts
View file

@ -67,6 +67,10 @@
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -175,6 +179,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l496zg/nucleo_l496zg.dts
View file

@ -62,6 +62,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -154,6 +158,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts
View file

@ -66,6 +66,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -172,6 +176,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts
View file

@ -89,6 +89,10 @@
status = "okay";
};
&clk_lsi1 {
status = "okay";
};
&clk_hse {
status = "okay";
};
@ -133,6 +137,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

2
boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts
View file

@ -137,6 +137,8 @@ uext_spi: &spi1 {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts
View file

@ -42,6 +42,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(12)>;
status = "okay";
@ -86,6 +90,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/olimex_stm32_h405/olimex_stm32_h405.dts
View file

@ -43,6 +43,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -73,6 +77,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/olimex_stm32_h407/olimex_stm32_h407.dts
View file

@ -42,6 +42,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(12)>;
status = "okay";
@ -86,6 +90,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/olimex_stm32_p405/olimex_stm32_p405.dts
View file

@ -43,6 +43,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -73,6 +77,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/ronoth_lodev/ronoth_lodev.dts
View file

@ -107,6 +107,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -163,6 +167,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.dts
View file

@ -41,6 +41,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(12)>;
status = "okay";
@ -64,6 +68,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/sensortile_box/sensortile_box.dts
View file

@ -51,6 +51,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
@ -174,6 +178,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/steval_fcu001v1/steval_fcu001v1.dts
View file

@ -39,6 +39,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
@ -86,6 +90,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32373c_eval/stm32373c_eval.dts
View file

@ -42,6 +42,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -70,6 +74,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f3_disco/stm32f3_disco.dts
View file

@ -74,6 +74,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -163,6 +167,8 @@ zephyr_udc0: &usb {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f401_mini/stm32f401_mini.dts
View file

@ -99,6 +99,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
@ -114,6 +116,10 @@ zephyr_udc0: &usbotg_fs {
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";

6
boards/arm/stm32f411e_disco/stm32f411e_disco.dts
View file

@ -78,6 +78,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -144,6 +148,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f412g_disco/stm32f412g_disco.dts
View file

@ -73,6 +73,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
@ -125,6 +129,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts
View file

@ -56,6 +56,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -86,6 +90,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f469i_disco/stm32f469i_disco.dts
View file

@ -58,6 +58,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -114,5 +118,7 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f4_disco/stm32f4_disco.dts
View file

@ -65,6 +65,10 @@
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
@ -105,6 +109,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f746g_disco/stm32f746g_disco.dts
View file

@ -55,6 +55,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
@ -136,6 +140,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32f7508_dk/stm32f7508_dk.dts
View file

@ -56,6 +56,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
@ -137,6 +141,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32l476g_disco/stm32l476g_disco.dts
View file

@ -65,6 +65,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -95,5 +99,7 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/stm32l496g_disco/stm32l496g_disco.dts
View file

@ -63,6 +63,10 @@
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -131,6 +135,8 @@
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};

6
boards/arm/swan_r5/swan_r5.dts
View file

@ -54,6 +54,10 @@
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
@ -161,6 +165,8 @@ zephyr_udc0: &usbotg_fs {
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};