2016-03-03 15:33:20 +01:00
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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2016-11-14 11:53:52 +01:00
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* Copyright (c) 2016 Linaro Limited.
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2016-03-03 15:33:20 +01:00
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*
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2017-01-18 17:01:01 -08:00
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* SPDX-License-Identifier: Apache-2.0
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2016-03-03 15:33:20 +01:00
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*/
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2020-03-24 14:28:48 -05:00
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#define DT_DRV_COMPAT st_stm32_uart
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2016-03-03 15:33:20 +01:00
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/**
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2018-03-20 20:44:45 +03:00
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* @brief Driver for UART port on STM32 family processor.
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2019-03-15 19:51:09 +01:00
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* @note LPUART and U(S)ART have the same base and
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* majority of operations are performed the same way.
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* Please validate for newly added series.
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2016-03-03 15:33:20 +01:00
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*/
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2016-12-04 14:59:37 -06:00
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#include <kernel.h>
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2016-03-03 15:33:20 +01:00
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#include <arch/cpu.h>
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2019-06-26 10:33:39 -04:00
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#include <sys/__assert.h>
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2018-10-31 12:44:45 -05:00
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#include <soc.h>
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2016-03-03 15:33:20 +01:00
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#include <init.h>
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2019-06-25 15:54:01 -04:00
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#include <drivers/uart.h>
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2019-06-25 15:53:47 -04:00
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#include <drivers/clock_control.h>
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2016-03-03 15:33:20 +01:00
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2017-06-17 11:30:47 -04:00
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#include <linker/sections.h>
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2020-01-25 05:34:53 -06:00
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#include <drivers/clock_control/stm32_clock_control.h>
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2016-03-03 15:33:20 +01:00
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#include "uart_stm32.h"
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2019-11-12 16:13:03 +01:00
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#include <logging/log.h>
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LOG_MODULE_REGISTER(uart_stm32);
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2020-05-07 12:22:26 -05:00
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#define HAS_LPUART_1 (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), \
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st_stm32_lpuart, okay))
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2020-04-17 12:33:29 +02:00
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2016-03-03 15:33:20 +01:00
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/* convenience defines */
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#define DEV_CFG(dev) \
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2020-05-28 20:44:16 +02:00
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((const struct uart_stm32_config * const)(dev)->config)
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2016-03-03 15:33:20 +01:00
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#define DEV_DATA(dev) \
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2020-05-28 21:23:02 +02:00
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((struct uart_stm32_data * const)(dev)->data)
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2016-03-03 15:33:20 +01:00
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#define UART_STRUCT(dev) \
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2016-11-14 11:53:52 +01:00
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((USART_TypeDef *)(DEV_CFG(dev))->uconf.base)
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2016-03-03 15:33:20 +01:00
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2016-11-14 11:53:52 +01:00
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#define TIMEOUT 1000
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2016-03-03 15:33:20 +01:00
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2020-04-30 20:33:38 +02:00
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static inline void uart_stm32_set_baudrate(const struct device *dev,
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uint32_t baud_rate)
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2019-01-07 13:52:24 -08:00
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{
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const struct uart_stm32_config *config = DEV_CFG(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2019-05-20 17:15:02 +02:00
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2020-05-27 11:26:57 -05:00
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uint32_t clock_rate;
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2019-01-07 13:52:24 -08:00
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/* Get clock rate */
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2019-11-12 16:13:03 +01:00
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if (clock_control_get_rate(data->clock,
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2019-01-07 13:52:24 -08:00
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(clock_control_subsys_t *)&config->pclken,
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2019-11-12 16:13:03 +01:00
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&clock_rate) < 0) {
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LOG_ERR("Failed call clock_control_get_rate");
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return;
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}
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2019-05-20 17:15:02 +02:00
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2020-04-17 12:33:29 +02:00
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#if HAS_LPUART_1
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2019-01-07 13:52:24 -08:00
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if (IS_LPUART_INSTANCE(UartInstance)) {
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2019-05-20 17:15:02 +02:00
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LL_LPUART_SetBaudRate(UartInstance,
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clock_rate,
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#ifdef USART_PRESC_PRESCALER
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LL_USART_PRESCALER_DIV1,
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#endif
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baud_rate);
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2019-01-07 13:52:24 -08:00
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} else {
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2020-04-17 12:33:29 +02:00
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#endif /* HAS_LPUART_1 */
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2019-05-20 17:15:02 +02:00
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LL_USART_SetBaudRate(UartInstance,
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clock_rate,
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#ifdef USART_PRESC_PRESCALER
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LL_USART_PRESCALER_DIV1,
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#endif
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#ifdef USART_CR1_OVER8
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LL_USART_OVERSAMPLING_16,
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2019-01-07 13:52:24 -08:00
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#endif
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2019-05-20 17:15:02 +02:00
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baud_rate);
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2020-04-17 12:33:29 +02:00
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#if HAS_LPUART_1
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2019-05-20 17:15:02 +02:00
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}
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2020-04-17 12:33:29 +02:00
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#endif /* HAS_LPUART_1 */
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2019-01-07 13:52:24 -08:00
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}
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2020-04-30 20:33:38 +02:00
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static inline void uart_stm32_set_parity(const struct device *dev,
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uint32_t parity)
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2019-01-07 13:52:24 -08:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_SetParity(UartInstance, parity);
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}
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2020-04-30 20:33:38 +02:00
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static inline uint32_t uart_stm32_get_parity(const struct device *dev)
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2019-01-07 13:52:24 -08:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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return LL_USART_GetParity(UartInstance);
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}
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2020-04-30 20:33:38 +02:00
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static inline void uart_stm32_set_stopbits(const struct device *dev,
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uint32_t stopbits)
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2019-01-07 13:52:24 -08:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_SetStopBitsLength(UartInstance, stopbits);
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}
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2020-04-30 20:33:38 +02:00
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static inline uint32_t uart_stm32_get_stopbits(const struct device *dev)
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2019-01-07 13:52:24 -08:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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return LL_USART_GetStopBitsLength(UartInstance);
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}
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2020-04-30 20:33:38 +02:00
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static inline void uart_stm32_set_databits(const struct device *dev,
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uint32_t databits)
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2019-01-07 13:52:24 -08:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_SetDataWidth(UartInstance, databits);
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}
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2020-04-30 20:33:38 +02:00
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static inline uint32_t uart_stm32_get_databits(const struct device *dev)
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2019-01-07 13:52:24 -08:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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return LL_USART_GetDataWidth(UartInstance);
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}
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2020-04-30 20:33:38 +02:00
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static inline void uart_stm32_set_hwctrl(const struct device *dev,
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uint32_t hwctrl)
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2019-03-15 19:51:09 +01:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_SetHWFlowCtrl(UartInstance, hwctrl);
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}
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2020-04-30 20:33:38 +02:00
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static inline uint32_t uart_stm32_get_hwctrl(const struct device *dev)
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2019-03-15 19:51:09 +01:00
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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return LL_USART_GetHWFlowCtrl(UartInstance);
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}
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2020-05-27 11:26:57 -05:00
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static inline uint32_t uart_stm32_cfg2ll_parity(enum uart_config_parity parity)
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2019-01-07 13:52:24 -08:00
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{
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switch (parity) {
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case UART_CFG_PARITY_ODD:
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return LL_USART_PARITY_ODD;
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case UART_CFG_PARITY_EVEN:
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return LL_USART_PARITY_EVEN;
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case UART_CFG_PARITY_NONE:
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default:
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return LL_USART_PARITY_NONE;
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}
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}
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2020-05-27 11:26:57 -05:00
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static inline enum uart_config_parity uart_stm32_ll2cfg_parity(uint32_t parity)
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2019-01-07 13:52:24 -08:00
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{
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switch (parity) {
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case LL_USART_PARITY_ODD:
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return UART_CFG_PARITY_ODD;
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case LL_USART_PARITY_EVEN:
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return UART_CFG_PARITY_EVEN;
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case LL_USART_PARITY_NONE:
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default:
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return UART_CFG_PARITY_NONE;
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}
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}
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2020-05-27 11:26:57 -05:00
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static inline uint32_t uart_stm32_cfg2ll_stopbits(enum uart_config_stop_bits sb)
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2019-01-07 13:52:24 -08:00
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{
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switch (sb) {
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/* Some MCU's don't support 0.5 stop bits */
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#ifdef LL_USART_STOPBITS_0_5
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case UART_CFG_STOP_BITS_0_5:
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return LL_USART_STOPBITS_0_5;
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#endif /* LL_USART_STOPBITS_0_5 */
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case UART_CFG_STOP_BITS_1:
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return LL_USART_STOPBITS_1;
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/* Some MCU's don't support 1.5 stop bits */
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#ifdef LL_USART_STOPBITS_1_5
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case UART_CFG_STOP_BITS_1_5:
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return LL_USART_STOPBITS_1_5;
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#endif /* LL_USART_STOPBITS_1_5 */
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case UART_CFG_STOP_BITS_2:
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default:
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return LL_USART_STOPBITS_2;
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}
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}
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2020-05-27 11:26:57 -05:00
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static inline enum uart_config_stop_bits uart_stm32_ll2cfg_stopbits(uint32_t sb)
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2019-01-07 13:52:24 -08:00
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{
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switch (sb) {
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/* Some MCU's don't support 0.5 stop bits */
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#ifdef LL_USART_STOPBITS_0_5
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case LL_USART_STOPBITS_0_5:
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return UART_CFG_STOP_BITS_0_5;
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#endif /* LL_USART_STOPBITS_0_5 */
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case LL_USART_STOPBITS_1:
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return UART_CFG_STOP_BITS_1;
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/* Some MCU's don't support 1.5 stop bits */
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#ifdef LL_USART_STOPBITS_1_5
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case LL_USART_STOPBITS_1_5:
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return UART_CFG_STOP_BITS_1_5;
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#endif /* LL_USART_STOPBITS_1_5 */
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case LL_USART_STOPBITS_2:
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default:
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return UART_CFG_STOP_BITS_2;
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}
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}
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2020-05-27 11:26:57 -05:00
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static inline uint32_t uart_stm32_cfg2ll_databits(enum uart_config_data_bits db)
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2019-01-07 13:52:24 -08:00
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{
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switch (db) {
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2019-03-22 14:19:57 +01:00
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/* Some MCU's don't support 7B or 9B datawidth */
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2019-01-07 13:52:24 -08:00
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#ifdef LL_USART_DATAWIDTH_7B
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case UART_CFG_DATA_BITS_7:
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return LL_USART_DATAWIDTH_7B;
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#endif /* LL_USART_DATAWIDTH_7B */
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2019-03-22 14:19:57 +01:00
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#ifdef LL_USART_DATAWIDTH_9B
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case UART_CFG_DATA_BITS_9:
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return LL_USART_DATAWIDTH_9B;
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#endif /* LL_USART_DATAWIDTH_9B */
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2019-01-07 13:52:24 -08:00
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case UART_CFG_DATA_BITS_8:
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default:
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return LL_USART_DATAWIDTH_8B;
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}
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}
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2020-05-27 11:26:57 -05:00
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static inline enum uart_config_data_bits uart_stm32_ll2cfg_databits(uint32_t db)
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2019-01-07 13:52:24 -08:00
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{
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switch (db) {
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2019-03-22 14:19:57 +01:00
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/* Some MCU's don't support 7B or 9B datawidth */
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2019-01-07 13:52:24 -08:00
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#ifdef LL_USART_DATAWIDTH_7B
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case LL_USART_DATAWIDTH_7B:
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return UART_CFG_DATA_BITS_7;
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#endif /* LL_USART_DATAWIDTH_7B */
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2019-03-22 14:19:57 +01:00
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#ifdef LL_USART_DATAWIDTH_9B
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case LL_USART_DATAWIDTH_9B:
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return UART_CFG_DATA_BITS_9;
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#endif /* LL_USART_DATAWIDTH_9B */
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2019-01-07 13:52:24 -08:00
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case LL_USART_DATAWIDTH_8B:
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default:
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return UART_CFG_DATA_BITS_8;
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}
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}
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2019-03-15 19:51:09 +01:00
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/**
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* @brief Get LL hardware flow control define from
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* Zephyr hardware flow control option.
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* @note Supports only UART_CFG_FLOW_CTRL_RTS_CTS.
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* @param fc: Zephyr hardware flow control option.
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* @retval LL_USART_HWCONTROL_RTS_CTS, or LL_USART_HWCONTROL_NONE.
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*/
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2020-05-27 11:26:57 -05:00
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static inline uint32_t uart_stm32_cfg2ll_hwctrl(enum uart_config_flow_control fc)
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2019-03-15 19:51:09 +01:00
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{
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if (fc == UART_CFG_FLOW_CTRL_RTS_CTS) {
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return LL_USART_HWCONTROL_RTS_CTS;
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}
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return LL_USART_HWCONTROL_NONE;
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}
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/**
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2020-02-06 20:36:03 +02:00
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* @brief Get Zephyr hardware flow control option from
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2019-03-15 19:51:09 +01:00
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* LL hardware flow control define.
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* @note Supports only LL_USART_HWCONTROL_RTS_CTS.
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2020-02-06 20:36:03 +02:00
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* @param fc: LL hardware flow control definition.
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2020-02-06 11:30:05 -06:00
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* @retval UART_CFG_FLOW_CTRL_RTS_CTS, or UART_CFG_FLOW_CTRL_NONE.
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2019-03-15 19:51:09 +01:00
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*/
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2020-05-27 11:26:57 -05:00
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static inline enum uart_config_flow_control uart_stm32_ll2cfg_hwctrl(uint32_t fc)
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2019-03-15 19:51:09 +01:00
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{
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if (fc == LL_USART_HWCONTROL_RTS_CTS) {
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return UART_CFG_FLOW_CTRL_RTS_CTS;
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}
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2020-02-06 11:30:05 -06:00
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return UART_CFG_FLOW_CTRL_NONE;
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2019-03-15 19:51:09 +01:00
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}
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2020-04-30 20:33:38 +02:00
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static int uart_stm32_configure(const struct device *dev,
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2019-01-07 13:52:24 -08:00
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const struct uart_config *cfg)
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{
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|
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2020-05-27 11:26:57 -05:00
|
|
|
const uint32_t parity = uart_stm32_cfg2ll_parity(cfg->parity);
|
|
|
|
const uint32_t stopbits = uart_stm32_cfg2ll_stopbits(cfg->stop_bits);
|
|
|
|
const uint32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits);
|
|
|
|
const uint32_t flowctrl = uart_stm32_cfg2ll_hwctrl(cfg->flow_ctrl);
|
2019-01-07 13:52:24 -08:00
|
|
|
|
|
|
|
/* Hardware doesn't support mark or space parity */
|
|
|
|
if ((UART_CFG_PARITY_MARK == cfg->parity) ||
|
|
|
|
(UART_CFG_PARITY_SPACE == cfg->parity)) {
|
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
|
|
|
|
2020-04-17 12:33:29 +02:00
|
|
|
#if defined(LL_USART_STOPBITS_0_5) && HAS_LPUART_1
|
2019-01-07 13:52:24 -08:00
|
|
|
if (IS_LPUART_INSTANCE(UartInstance) &&
|
|
|
|
UART_CFG_STOP_BITS_0_5 == cfg->stop_bits) {
|
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (UART_CFG_STOP_BITS_0_5 == cfg->stop_bits) {
|
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2020-04-17 12:33:29 +02:00
|
|
|
#if defined(LL_USART_STOPBITS_1_5) && HAS_LPUART_1
|
2019-01-07 13:52:24 -08:00
|
|
|
if (IS_LPUART_INSTANCE(UartInstance) &&
|
|
|
|
UART_CFG_STOP_BITS_1_5 == cfg->stop_bits) {
|
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (UART_CFG_STOP_BITS_1_5 == cfg->stop_bits) {
|
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2019-03-22 14:19:57 +01:00
|
|
|
/* Driver doesn't support 5 or 6 databits and potentially 7 or 9 */
|
2019-01-07 13:52:24 -08:00
|
|
|
if ((UART_CFG_DATA_BITS_5 == cfg->data_bits) ||
|
|
|
|
(UART_CFG_DATA_BITS_6 == cfg->data_bits)
|
|
|
|
#ifndef LL_USART_DATAWIDTH_7B
|
|
|
|
|| (UART_CFG_DATA_BITS_7 == cfg->data_bits)
|
|
|
|
#endif /* LL_USART_DATAWIDTH_7B */
|
2019-03-22 14:19:57 +01:00
|
|
|
#ifndef LL_USART_DATAWIDTH_9B
|
|
|
|
|| (UART_CFG_DATA_BITS_9 == cfg->data_bits)
|
|
|
|
#endif /* LL_USART_DATAWIDTH_9B */
|
2019-01-07 13:52:24 -08:00
|
|
|
) {
|
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
|
|
|
|
2019-03-15 19:51:09 +01:00
|
|
|
/* Driver supports only RTS CTS flow control */
|
2019-01-07 13:52:24 -08:00
|
|
|
if (UART_CFG_FLOW_CTRL_NONE != cfg->flow_ctrl) {
|
2019-03-15 19:51:09 +01:00
|
|
|
if (!IS_UART_HWFLOW_INSTANCE(UartInstance) ||
|
|
|
|
UART_CFG_FLOW_CTRL_RTS_CTS != cfg->flow_ctrl) {
|
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
2019-01-07 13:52:24 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
LL_USART_Disable(UartInstance);
|
|
|
|
|
|
|
|
if (parity != uart_stm32_get_parity(dev)) {
|
|
|
|
uart_stm32_set_parity(dev, parity);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stopbits != uart_stm32_get_stopbits(dev)) {
|
|
|
|
uart_stm32_set_stopbits(dev, stopbits);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (databits != uart_stm32_get_databits(dev)) {
|
|
|
|
uart_stm32_set_databits(dev, databits);
|
|
|
|
}
|
|
|
|
|
2019-03-15 19:51:09 +01:00
|
|
|
if (flowctrl != uart_stm32_get_hwctrl(dev)) {
|
|
|
|
uart_stm32_set_hwctrl(dev, flowctrl);
|
|
|
|
}
|
|
|
|
|
2019-01-07 13:52:24 -08:00
|
|
|
if (cfg->baudrate != data->baud_rate) {
|
|
|
|
uart_stm32_set_baudrate(dev, cfg->baudrate);
|
|
|
|
data->baud_rate = cfg->baudrate;
|
|
|
|
}
|
|
|
|
|
|
|
|
LL_USART_Enable(UartInstance);
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_config_get(const struct device *dev,
|
|
|
|
struct uart_config *cfg)
|
2019-01-07 13:52:24 -08:00
|
|
|
{
|
|
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
|
|
|
|
|
|
|
cfg->baudrate = data->baud_rate;
|
|
|
|
cfg->parity = uart_stm32_ll2cfg_parity(uart_stm32_get_parity(dev));
|
|
|
|
cfg->stop_bits = uart_stm32_ll2cfg_stopbits(
|
|
|
|
uart_stm32_get_stopbits(dev));
|
|
|
|
cfg->data_bits = uart_stm32_ll2cfg_databits(
|
|
|
|
uart_stm32_get_databits(dev));
|
2019-03-15 19:51:09 +01:00
|
|
|
cfg->flow_ctrl = uart_stm32_ll2cfg_hwctrl(
|
|
|
|
uart_stm32_get_hwctrl(dev));
|
2019-01-07 13:52:24 -08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_poll_in(const struct device *dev, unsigned char *c)
|
2016-03-03 15:33:20 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2018-11-02 15:34:56 +02:00
|
|
|
/* Clear overrun error flag */
|
|
|
|
if (LL_USART_IsActiveFlag_ORE(UartInstance)) {
|
|
|
|
LL_USART_ClearFlag_ORE(UartInstance);
|
|
|
|
}
|
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
if (!LL_USART_IsActiveFlag_RXNE(UartInstance)) {
|
2016-03-03 15:33:20 +01:00
|
|
|
return -1;
|
|
|
|
}
|
2017-09-21 15:20:53 +02:00
|
|
|
|
|
|
|
*c = (unsigned char)LL_USART_ReceiveData8(UartInstance);
|
|
|
|
|
|
|
|
return 0;
|
2016-03-03 15:33:20 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_poll_out(const struct device *dev,
|
2016-03-03 15:33:20 +01:00
|
|
|
unsigned char c)
|
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
/* Wait for TXE flag to be raised */
|
2019-06-04 10:52:23 -04:00
|
|
|
while (!LL_USART_IsActiveFlag_TXE(UartInstance)) {
|
|
|
|
}
|
2017-09-21 15:20:53 +02:00
|
|
|
|
|
|
|
LL_USART_ClearFlag_TC(UartInstance);
|
|
|
|
|
2020-05-27 11:26:57 -05:00
|
|
|
LL_USART_TransmitData8(UartInstance, (uint8_t)c);
|
2016-03-03 15:33:20 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_err_check(const struct device *dev)
|
2019-02-14 10:50:19 +01:00
|
|
|
{
|
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2020-05-27 11:26:57 -05:00
|
|
|
uint32_t err = 0U;
|
2019-02-14 10:50:19 +01:00
|
|
|
|
|
|
|
/* Check for errors, but don't clear them here.
|
|
|
|
* Some SoC clear all error flags when at least
|
|
|
|
* one is cleared. (e.g. F4X, F1X, and F2X)
|
|
|
|
*/
|
|
|
|
if (LL_USART_IsActiveFlag_ORE(UartInstance)) {
|
|
|
|
err |= UART_ERROR_OVERRUN;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (LL_USART_IsActiveFlag_PE(UartInstance)) {
|
|
|
|
err |= UART_ERROR_PARITY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (LL_USART_IsActiveFlag_FE(UartInstance)) {
|
|
|
|
err |= UART_ERROR_FRAMING;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (err & UART_ERROR_OVERRUN) {
|
|
|
|
LL_USART_ClearFlag_ORE(UartInstance);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (err & UART_ERROR_PARITY) {
|
|
|
|
LL_USART_ClearFlag_PE(UartInstance);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (err & UART_ERROR_FRAMING) {
|
|
|
|
LL_USART_ClearFlag_FE(UartInstance);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear noise error as well,
|
|
|
|
* it is not represented by the errors enum
|
|
|
|
*/
|
|
|
|
LL_USART_ClearFlag_NE(UartInstance);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static inline void __uart_stm32_get_clock(const struct device *dev)
|
2016-03-03 15:33:20 +01:00
|
|
|
{
|
2016-11-14 11:53:52 +01:00
|
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
2020-04-30 20:33:38 +02:00
|
|
|
const struct device *clk =
|
2016-03-03 15:33:20 +01:00
|
|
|
device_get_binding(STM32_CLOCK_CONTROL_NAME);
|
|
|
|
|
|
|
|
__ASSERT_NO_MSG(clk);
|
|
|
|
|
2016-11-14 11:53:52 +01:00
|
|
|
data->clock = clk;
|
2016-03-03 15:33:20 +01:00
|
|
|
}
|
|
|
|
|
2016-03-13 19:37:25 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_fifo_fill(const struct device *dev,
|
|
|
|
const uint8_t *tx_data,
|
2016-03-13 19:37:25 +01:00
|
|
|
int size)
|
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2020-05-27 11:26:57 -05:00
|
|
|
uint8_t num_tx = 0U;
|
2016-11-14 11:53:52 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
while ((size - num_tx > 0) &&
|
|
|
|
LL_USART_IsActiveFlag_TXE(UartInstance)) {
|
2019-02-06 23:31:24 +01:00
|
|
|
/* TXE flag will be cleared with byte write to DR|RDR register */
|
2016-11-14 11:53:52 +01:00
|
|
|
|
|
|
|
/* Send a character (8bit , parity none) */
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_TransmitData8(UartInstance, tx_data[num_tx++]);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return num_tx;
|
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_fifo_read(const struct device *dev, uint8_t *rx_data,
|
2016-03-13 19:37:25 +01:00
|
|
|
const int size)
|
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2020-05-27 11:26:57 -05:00
|
|
|
uint8_t num_rx = 0U;
|
2016-11-14 11:53:52 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
while ((size - num_rx > 0) &&
|
|
|
|
LL_USART_IsActiveFlag_RXNE(UartInstance)) {
|
2019-02-06 23:31:24 +01:00
|
|
|
/* RXNE flag will be cleared upon read from DR|RDR register */
|
2016-11-14 11:53:52 +01:00
|
|
|
|
|
|
|
/* Receive a character (8bit , parity none) */
|
2017-09-21 15:20:53 +02:00
|
|
|
rx_data[num_rx++] = LL_USART_ReceiveData8(UartInstance);
|
2018-11-02 15:34:56 +02:00
|
|
|
|
|
|
|
/* Clear overrun error flag */
|
|
|
|
if (LL_USART_IsActiveFlag_ORE(UartInstance)) {
|
|
|
|
LL_USART_ClearFlag_ORE(UartInstance);
|
|
|
|
}
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
2019-02-06 23:31:24 +01:00
|
|
|
|
2016-03-13 19:37:25 +01:00
|
|
|
return num_rx;
|
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_tx_enable(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_EnableIT_TC(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_tx_disable(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_DisableIT_TC(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_irq_tx_ready(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
return LL_USART_IsActiveFlag_TXE(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_irq_tx_complete(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2019-09-25 19:57:35 +02:00
|
|
|
return LL_USART_IsActiveFlag_TC(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_rx_enable(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_EnableIT_RXNE(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_rx_disable(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_DisableIT_RXNE(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_irq_rx_ready(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
return LL_USART_IsActiveFlag_RXNE(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_err_enable(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-11-14 11:53:52 +01:00
|
|
|
|
|
|
|
/* Enable FE, ORE interruptions */
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_EnableIT_ERROR(UartInstance);
|
2018-03-29 19:40:00 +03:00
|
|
|
#if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT)
|
2016-11-14 11:53:52 +01:00
|
|
|
/* Enable Line break detection */
|
2018-03-29 19:40:00 +03:00
|
|
|
if (IS_UART_LIN_INSTANCE(UartInstance)) {
|
|
|
|
LL_USART_EnableIT_LBD(UartInstance);
|
|
|
|
}
|
2017-08-09 11:23:04 +02:00
|
|
|
#endif
|
2016-11-14 11:53:52 +01:00
|
|
|
/* Enable parity error interruption */
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_EnableIT_PE(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_err_disable(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
|
|
|
|
2018-03-29 19:40:00 +03:00
|
|
|
/* Disable FE, ORE interruptions */
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_DisableIT_ERROR(UartInstance);
|
2018-03-29 19:40:00 +03:00
|
|
|
#if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT)
|
|
|
|
/* Disable Line break detection */
|
|
|
|
if (IS_UART_LIN_INSTANCE(UartInstance)) {
|
|
|
|
LL_USART_DisableIT_LBD(UartInstance);
|
|
|
|
}
|
2017-08-09 11:23:04 +02:00
|
|
|
#endif
|
2018-03-29 19:40:00 +03:00
|
|
|
/* Disable parity error interruption */
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_DisableIT_PE(UartInstance);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_irq_is_pending(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-12-05 13:46:13 -06:00
|
|
|
return ((LL_USART_IsActiveFlag_RXNE(UartInstance) &&
|
|
|
|
LL_USART_IsEnabledIT_RXNE(UartInstance)) ||
|
2018-11-13 15:26:06 +01:00
|
|
|
(LL_USART_IsActiveFlag_TC(UartInstance) &&
|
|
|
|
LL_USART_IsEnabledIT_TC(UartInstance)));
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_irq_update(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_callback_set(const struct device *dev,
|
2018-07-16 21:12:26 +03:00
|
|
|
uart_irq_callback_user_data_t cb,
|
|
|
|
void *cb_data)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
|
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
|
|
|
|
|
|
|
data->user_cb = cb;
|
2018-07-16 21:12:26 +03:00
|
|
|
data->user_data = cb_data;
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
|
isr: Normalize usage of device instance through ISR
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs
This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.
Note that only the ISR passed to IRQ_CONNECT are of interest here.
In order to do so, the script fix_isr.py below is necessary:
from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os
cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
(
const struct device *D = (const struct device *)P;
|
const struct device *D = P;
)
...
}
@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
const struct device *D;
...
(
D = (const struct device *)P;
|
D = P;
)
...
}
@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
...
}
@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);
@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
...
}
@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
...
}
"""
def find_isr(fn):
db = []
data = None
start = 0
try:
with open(fn, 'r+') as f:
data = str(mmap.mmap(f.fileno(), 0).read())
except Exception as e:
return db
while True:
isr = ""
irq = data.find('IRQ_CONNECT', start)
while irq > -1:
p = 1
arg = 1
p_o = data.find('(', irq)
if p_o < 0:
irq = -1
break;
pos = p_o + 1
while p > 0:
if data[pos] == ')':
p -= 1
elif data[pos] == '(':
p += 1
elif data[pos] == ',' and p == 1:
arg += 1
if arg == 3:
isr += data[pos]
pos += 1
isr = isr.strip(',\\n\\t ')
if isr not in db and len(isr) > 0:
db.append(isr)
start = pos
break
if irq < 0:
break
return db
def patch_isr(fn, isr_list):
if len(isr_list) <= 0:
return
for isr in isr_list:
tmplt = cocci_template.replace('<!fn!>', isr)
with open('/tmp/isr_fix.cocci', 'w') as f:
f.write(tmplt)
cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]
subprocess.run(cmd)
def process_files(path):
if path.is_file() and path.suffix in ['.h', '.c']:
p = str(path.parent) + '/' + path.name
isr_list = find_isr(p)
patch_isr(p, isr_list)
elif path.is_dir():
for p in path.iterdir():
process_files(p)
if len(sys.argv) < 2:
print("You need to provide a dir/file path")
sys.exit(1)
process_files(Path(sys.argv[1]))
And is run: ./fix_isr.py <zephyr root directory>
Finally, some files needed manual fixes such.
Fixes #27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-06-17 14:58:56 +02:00
|
|
|
static void uart_stm32_isr(const struct device *dev)
|
2016-03-13 19:37:25 +01:00
|
|
|
{
|
|
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
|
|
|
|
|
|
|
if (data->user_cb) {
|
2020-06-24 15:47:15 +02:00
|
|
|
data->user_cb(dev, data->user_data);
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
|
2016-10-24 08:38:49 +01:00
|
|
|
static const struct uart_driver_api uart_stm32_driver_api = {
|
2016-03-03 15:33:20 +01:00
|
|
|
.poll_in = uart_stm32_poll_in,
|
|
|
|
.poll_out = uart_stm32_poll_out,
|
2019-02-14 10:50:19 +01:00
|
|
|
.err_check = uart_stm32_err_check,
|
2019-01-07 13:52:24 -08:00
|
|
|
.configure = uart_stm32_configure,
|
|
|
|
.config_get = uart_stm32_config_get,
|
2016-03-13 19:37:25 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
|
|
.fifo_fill = uart_stm32_fifo_fill,
|
|
|
|
.fifo_read = uart_stm32_fifo_read,
|
|
|
|
.irq_tx_enable = uart_stm32_irq_tx_enable,
|
|
|
|
.irq_tx_disable = uart_stm32_irq_tx_disable,
|
|
|
|
.irq_tx_ready = uart_stm32_irq_tx_ready,
|
2017-05-11 17:57:29 +03:00
|
|
|
.irq_tx_complete = uart_stm32_irq_tx_complete,
|
2016-03-13 19:37:25 +01:00
|
|
|
.irq_rx_enable = uart_stm32_irq_rx_enable,
|
|
|
|
.irq_rx_disable = uart_stm32_irq_rx_disable,
|
|
|
|
.irq_rx_ready = uart_stm32_irq_rx_ready,
|
|
|
|
.irq_err_enable = uart_stm32_irq_err_enable,
|
|
|
|
.irq_err_disable = uart_stm32_irq_err_disable,
|
|
|
|
.irq_is_pending = uart_stm32_irq_is_pending,
|
|
|
|
.irq_update = uart_stm32_irq_update,
|
|
|
|
.irq_callback_set = uart_stm32_irq_callback_set,
|
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
2016-03-03 15:33:20 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Initialize UART channel
|
|
|
|
*
|
|
|
|
* This routine is called to reset the chip in a quiescent state.
|
|
|
|
* It is assumed that this function is called only once per UART.
|
|
|
|
*
|
|
|
|
* @param dev UART device struct
|
|
|
|
*
|
|
|
|
* @return 0
|
|
|
|
*/
|
2020-04-30 20:33:38 +02:00
|
|
|
static int uart_stm32_init(const struct device *dev)
|
2016-03-03 15:33:20 +01:00
|
|
|
{
|
2016-11-14 11:53:52 +01:00
|
|
|
const struct uart_stm32_config *config = DEV_CFG(dev);
|
2016-03-03 15:33:20 +01:00
|
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
2017-09-21 15:20:53 +02:00
|
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
2020-05-27 11:26:57 -05:00
|
|
|
uint32_t ll_parity;
|
|
|
|
uint32_t ll_datawidth;
|
2017-09-21 15:20:53 +02:00
|
|
|
|
2016-03-03 15:33:20 +01:00
|
|
|
__uart_stm32_get_clock(dev);
|
|
|
|
/* enable clock */
|
2018-12-07 11:09:28 +01:00
|
|
|
if (clock_control_on(data->clock,
|
|
|
|
(clock_control_subsys_t *)&config->pclken) != 0) {
|
|
|
|
return -EIO;
|
|
|
|
}
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_Disable(UartInstance);
|
|
|
|
|
|
|
|
/* TX/RX direction */
|
|
|
|
LL_USART_SetTransferDirection(UartInstance,
|
|
|
|
LL_USART_DIRECTION_TX_RX);
|
|
|
|
|
2020-03-18 13:40:21 +02:00
|
|
|
/* Determine the datawidth and parity. If we use other parity than
|
|
|
|
* 'none' we must use datawidth = 9 (to get 8 databit + 1 parity bit).
|
|
|
|
*/
|
|
|
|
if (config->parity == 2) {
|
|
|
|
/* 8 databit, 1 parity bit, parity even */
|
|
|
|
ll_parity = LL_USART_PARITY_EVEN;
|
|
|
|
ll_datawidth = LL_USART_DATAWIDTH_9B;
|
|
|
|
} else if (config->parity == 1) {
|
|
|
|
/* 8 databit, 1 parity bit, parity odd */
|
|
|
|
ll_parity = LL_USART_PARITY_ODD;
|
|
|
|
ll_datawidth = LL_USART_DATAWIDTH_9B;
|
|
|
|
} else { /* Default to 8N0, but show warning if invalid value */
|
|
|
|
if (config->parity != 0) {
|
|
|
|
LOG_WRN("Invalid parity setting '%d'."
|
|
|
|
"Defaulting to 'none'.", config->parity);
|
|
|
|
}
|
|
|
|
/* 8 databit, parity none */
|
|
|
|
ll_parity = LL_USART_PARITY_NONE;
|
|
|
|
ll_datawidth = LL_USART_DATAWIDTH_8B;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set datawidth and parity, 1 start bit, 1 stop bit */
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_ConfigCharacter(UartInstance,
|
2020-03-18 13:40:21 +02:00
|
|
|
ll_datawidth,
|
|
|
|
ll_parity,
|
2017-09-21 15:20:53 +02:00
|
|
|
LL_USART_STOPBITS_1);
|
|
|
|
|
2019-02-08 18:39:35 +01:00
|
|
|
if (config->hw_flow_control) {
|
|
|
|
uart_stm32_set_hwctrl(dev, LL_USART_HWCONTROL_RTS_CTS);
|
|
|
|
}
|
|
|
|
|
2019-01-07 13:52:24 -08:00
|
|
|
/* Set the default baudrate */
|
|
|
|
uart_stm32_set_baudrate(dev, data->baud_rate);
|
2017-09-21 15:20:53 +02:00
|
|
|
|
|
|
|
LL_USART_Enable(UartInstance);
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2018-06-13 11:32:38 +02:00
|
|
|
#ifdef USART_ISR_TEACK
|
|
|
|
/* Wait until TEACK flag is set */
|
2019-06-04 10:52:23 -04:00
|
|
|
while (!(LL_USART_IsActiveFlag_TEACK(UartInstance))) {
|
|
|
|
}
|
2018-06-13 11:32:38 +02:00
|
|
|
#endif /* !USART_ISR_TEACK */
|
|
|
|
|
|
|
|
#ifdef USART_ISR_REACK
|
2018-06-18 18:01:06 +02:00
|
|
|
/* Wait until REACK flag is set */
|
2019-06-04 10:52:23 -04:00
|
|
|
while (!(LL_USART_IsActiveFlag_REACK(UartInstance))) {
|
|
|
|
}
|
2018-06-13 11:32:38 +02:00
|
|
|
#endif /* !USART_ISR_REACK */
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2016-03-13 19:37:25 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2016-11-14 11:53:52 +01:00
|
|
|
config->uconf.irq_config_func(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
#endif
|
2016-03-03 15:33:20 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2016-03-13 19:37:25 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2020-02-28 14:54:37 +01:00
|
|
|
#define STM32_UART_IRQ_HANDLER_DECL(index) \
|
2020-07-14 17:02:00 +02:00
|
|
|
static void uart_stm32_irq_config_func_##index(const struct device *dev)
|
2020-02-28 14:54:37 +01:00
|
|
|
#define STM32_UART_IRQ_HANDLER_FUNC(index) \
|
|
|
|
.irq_config_func = uart_stm32_irq_config_func_##index,
|
|
|
|
#define STM32_UART_IRQ_HANDLER(index) \
|
2020-04-30 20:33:38 +02:00
|
|
|
static void uart_stm32_irq_config_func_##index(const struct device *dev) \
|
2017-05-01 15:21:52 +02:00
|
|
|
{ \
|
2020-03-24 14:28:48 -05:00
|
|
|
IRQ_CONNECT(DT_INST_IRQN(index), \
|
|
|
|
DT_INST_IRQ(index, priority), \
|
2020-02-28 14:54:37 +01:00
|
|
|
uart_stm32_isr, DEVICE_GET(uart_stm32_##index), \
|
2017-05-01 15:21:52 +02:00
|
|
|
0); \
|
2020-03-24 14:28:48 -05:00
|
|
|
irq_enable(DT_INST_IRQN(index)); \
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
2017-01-23 17:55:57 +01:00
|
|
|
#else
|
2020-02-28 14:54:37 +01:00
|
|
|
#define STM32_UART_IRQ_HANDLER_DECL(index)
|
|
|
|
#define STM32_UART_IRQ_HANDLER_FUNC(index)
|
|
|
|
#define STM32_UART_IRQ_HANDLER(index)
|
2017-05-01 15:21:52 +02:00
|
|
|
#endif
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2020-02-28 14:54:37 +01:00
|
|
|
#define STM32_UART_INIT(index) \
|
|
|
|
STM32_UART_IRQ_HANDLER_DECL(index); \
|
2017-05-01 15:21:52 +02:00
|
|
|
\
|
2020-02-28 14:54:37 +01:00
|
|
|
static const struct uart_stm32_config uart_stm32_cfg_##index = { \
|
2017-05-01 15:21:52 +02:00
|
|
|
.uconf = { \
|
2020-05-27 11:26:57 -05:00
|
|
|
.base = (uint8_t *)DT_INST_REG_ADDR(index),\
|
2020-02-28 14:54:37 +01:00
|
|
|
STM32_UART_IRQ_HANDLER_FUNC(index) \
|
2017-05-01 15:21:52 +02:00
|
|
|
}, \
|
2020-03-24 14:28:48 -05:00
|
|
|
.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \
|
|
|
|
.enr = DT_INST_CLOCKS_CELL(index, bits) \
|
2018-11-08 14:38:48 +01:00
|
|
|
}, \
|
2020-03-18 13:40:21 +02:00
|
|
|
.hw_flow_control = DT_INST_PROP(index, hw_flow_control),\
|
|
|
|
.parity = DT_INST_PROP(index, parity)\
|
2017-05-01 15:21:52 +02:00
|
|
|
}; \
|
|
|
|
\
|
2020-02-28 14:54:37 +01:00
|
|
|
static struct uart_stm32_data uart_stm32_data_##index = { \
|
2020-03-24 14:28:48 -05:00
|
|
|
.baud_rate = DT_INST_PROP(index, current_speed) \
|
2017-05-01 15:21:52 +02:00
|
|
|
}; \
|
|
|
|
\
|
2020-03-24 14:28:48 -05:00
|
|
|
DEVICE_AND_API_INIT(uart_stm32_##index, DT_INST_LABEL(index),\
|
2017-05-01 15:21:52 +02:00
|
|
|
&uart_stm32_init, \
|
2020-02-28 14:54:37 +01:00
|
|
|
&uart_stm32_data_##index, &uart_stm32_cfg_##index, \
|
2017-05-01 15:21:52 +02:00
|
|
|
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
|
|
&uart_stm32_driver_api); \
|
|
|
|
\
|
2020-02-28 14:54:37 +01:00
|
|
|
STM32_UART_IRQ_HANDLER(index)
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2020-05-06 11:23:07 -07:00
|
|
|
DT_INST_FOREACH_STATUS_OKAY(STM32_UART_INIT)
|