2016-03-03 15:33:20 +01:00
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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2016-11-14 11:53:52 +01:00
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* Copyright (c) 2016 Linaro Limited.
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2016-03-03 15:33:20 +01:00
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*
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2017-01-18 17:01:01 -08:00
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* SPDX-License-Identifier: Apache-2.0
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2016-03-03 15:33:20 +01:00
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*/
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/**
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2018-03-20 20:44:45 +03:00
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* @brief Driver for UART port on STM32 family processor.
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2016-03-03 15:33:20 +01:00
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*
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*/
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2016-12-04 14:59:37 -06:00
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#include <kernel.h>
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2016-03-03 15:33:20 +01:00
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <init.h>
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#include <uart.h>
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#include <clock_control.h>
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2017-06-17 11:30:47 -04:00
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#include <linker/sections.h>
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2016-03-03 15:33:20 +01:00
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#include <clock_control/stm32_clock_control.h>
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#include "uart_stm32.h"
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/* convenience defines */
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#define DEV_CFG(dev) \
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2016-10-06 19:47:13 +01:00
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((const struct uart_stm32_config * const)(dev)->config->config_info)
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2016-03-03 15:33:20 +01:00
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#define DEV_DATA(dev) \
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((struct uart_stm32_data * const)(dev)->driver_data)
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#define UART_STRUCT(dev) \
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2016-11-14 11:53:52 +01:00
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((USART_TypeDef *)(DEV_CFG(dev))->uconf.base)
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2016-03-03 15:33:20 +01:00
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2016-11-14 11:53:52 +01:00
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#define TIMEOUT 1000
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2016-03-03 15:33:20 +01:00
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static int uart_stm32_poll_in(struct device *dev, unsigned char *c)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-03 15:33:20 +01:00
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2017-09-21 15:20:53 +02:00
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if (!LL_USART_IsActiveFlag_RXNE(UartInstance)) {
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2016-03-03 15:33:20 +01:00
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return -1;
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}
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2017-09-21 15:20:53 +02:00
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*c = (unsigned char)LL_USART_ReceiveData8(UartInstance);
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return 0;
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2016-03-03 15:33:20 +01:00
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}
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static unsigned char uart_stm32_poll_out(struct device *dev,
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unsigned char c)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-03 15:33:20 +01:00
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2017-09-21 15:20:53 +02:00
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/* Wait for TXE flag to be raised */
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while (!LL_USART_IsActiveFlag_TXE(UartInstance))
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;
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LL_USART_ClearFlag_TC(UartInstance);
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LL_USART_TransmitData8(UartInstance, (u8_t)c);
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2016-03-03 15:33:20 +01:00
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return c;
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}
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static inline void __uart_stm32_get_clock(struct device *dev)
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{
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2016-11-14 11:53:52 +01:00
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struct uart_stm32_data *data = DEV_DATA(dev);
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2016-03-03 15:33:20 +01:00
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struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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2016-11-14 11:53:52 +01:00
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data->clock = clk;
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2016-03-03 15:33:20 +01:00
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}
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2016-03-13 19:37:25 +01:00
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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2017-04-21 10:03:20 -05:00
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static int uart_stm32_fifo_fill(struct device *dev, const u8_t *tx_data,
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2016-03-13 19:37:25 +01:00
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int size)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2017-04-21 10:03:20 -05:00
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u8_t num_tx = 0;
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2016-11-14 11:53:52 +01:00
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2017-09-21 15:20:53 +02:00
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while ((size - num_tx > 0) &&
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LL_USART_IsActiveFlag_TXE(UartInstance)) {
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2016-11-14 11:53:52 +01:00
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/* TXE flag will be cleared with byte write to DR register */
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/* Send a character (8bit , parity none) */
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2017-09-21 15:20:53 +02:00
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LL_USART_TransmitData8(UartInstance, tx_data[num_tx++]);
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2016-03-13 19:37:25 +01:00
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}
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return num_tx;
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}
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2017-04-21 10:03:20 -05:00
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static int uart_stm32_fifo_read(struct device *dev, u8_t *rx_data,
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2016-03-13 19:37:25 +01:00
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const int size)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2017-04-21 10:03:20 -05:00
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u8_t num_rx = 0;
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2016-11-14 11:53:52 +01:00
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2017-09-21 15:20:53 +02:00
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while ((size - num_rx > 0) &&
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LL_USART_IsActiveFlag_RXNE(UartInstance)) {
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X)
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2016-11-14 11:53:52 +01:00
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/* Clear the interrupt */
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2017-09-21 15:20:53 +02:00
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LL_USART_ClearFlag_RXNE(UartInstance);
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#endif
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2016-11-14 11:53:52 +01:00
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/* Receive a character (8bit , parity none) */
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2017-09-21 15:20:53 +02:00
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rx_data[num_rx++] = LL_USART_ReceiveData8(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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return num_rx;
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}
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static void uart_stm32_irq_tx_enable(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-09-21 15:20:53 +02:00
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LL_USART_EnableIT_TC(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static void uart_stm32_irq_tx_disable(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-09-21 15:20:53 +02:00
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LL_USART_DisableIT_TC(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static int uart_stm32_irq_tx_ready(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-09-21 15:20:53 +02:00
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return LL_USART_IsActiveFlag_TXE(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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2017-05-11 17:57:29 +03:00
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static int uart_stm32_irq_tx_complete(struct device *dev)
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2016-03-13 19:37:25 +01:00
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-09-21 15:20:53 +02:00
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return LL_USART_IsActiveFlag_TXE(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static void uart_stm32_irq_rx_enable(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-09-21 15:20:53 +02:00
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LL_USART_EnableIT_RXNE(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static void uart_stm32_irq_rx_disable(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-09-21 15:20:53 +02:00
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LL_USART_DisableIT_RXNE(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static int uart_stm32_irq_rx_ready(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-09-21 15:20:53 +02:00
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return LL_USART_IsActiveFlag_RXNE(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static void uart_stm32_irq_err_enable(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-11-14 11:53:52 +01:00
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/* Enable FE, ORE interruptions */
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2017-09-21 15:20:53 +02:00
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LL_USART_EnableIT_ERROR(UartInstance);
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2016-11-14 11:53:52 +01:00
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/* Enable Line break detection */
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2017-10-27 17:20:40 +02:00
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#ifndef CONFIG_SOC_SERIES_STM32F0X
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2017-09-21 15:20:53 +02:00
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LL_USART_EnableIT_LBD(UartInstance);
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2017-08-09 11:23:04 +02:00
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#endif
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2016-11-14 11:53:52 +01:00
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/* Enable parity error interruption */
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2017-09-21 15:20:53 +02:00
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LL_USART_EnableIT_PE(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static void uart_stm32_irq_err_disable(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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/* Enable FE, ORE interruptions */
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LL_USART_DisableIT_ERROR(UartInstance);
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/* Enable Line break detection */
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2017-10-27 17:20:40 +02:00
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#ifndef CONFIG_SOC_SERIES_STM32F0X
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2017-09-21 15:20:53 +02:00
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LL_USART_DisableIT_LBD(UartInstance);
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2017-08-09 11:23:04 +02:00
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#endif
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2017-09-21 15:20:53 +02:00
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/* Enable parity error interruption */
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LL_USART_DisableIT_PE(UartInstance);
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2016-03-13 19:37:25 +01:00
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}
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static int uart_stm32_irq_is_pending(struct device *dev)
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{
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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2016-03-13 19:37:25 +01:00
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2017-12-05 13:46:13 -06:00
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return ((LL_USART_IsActiveFlag_RXNE(UartInstance) &&
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LL_USART_IsEnabledIT_RXNE(UartInstance)) ||
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(LL_USART_IsActiveFlag_TXE(UartInstance) &&
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LL_USART_IsEnabledIT_TXE(UartInstance)));
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2016-03-13 19:37:25 +01:00
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}
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static int uart_stm32_irq_update(struct device *dev)
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{
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return 1;
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}
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static void uart_stm32_irq_callback_set(struct device *dev,
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2016-11-14 11:53:52 +01:00
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uart_irq_callback_t cb)
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2016-03-13 19:37:25 +01:00
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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data->user_cb = cb;
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}
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static void uart_stm32_isr(void *arg)
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{
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struct device *dev = arg;
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struct uart_stm32_data *data = DEV_DATA(dev);
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if (data->user_cb) {
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data->user_cb(dev);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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2016-10-24 08:38:49 +01:00
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static const struct uart_driver_api uart_stm32_driver_api = {
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2016-03-03 15:33:20 +01:00
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.poll_in = uart_stm32_poll_in,
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.poll_out = uart_stm32_poll_out,
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2016-03-13 19:37:25 +01:00
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_stm32_fifo_fill,
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.fifo_read = uart_stm32_fifo_read,
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.irq_tx_enable = uart_stm32_irq_tx_enable,
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.irq_tx_disable = uart_stm32_irq_tx_disable,
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.irq_tx_ready = uart_stm32_irq_tx_ready,
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2017-05-11 17:57:29 +03:00
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.irq_tx_complete = uart_stm32_irq_tx_complete,
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2016-03-13 19:37:25 +01:00
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.irq_rx_enable = uart_stm32_irq_rx_enable,
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.irq_rx_disable = uart_stm32_irq_rx_disable,
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.irq_rx_ready = uart_stm32_irq_rx_ready,
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.irq_err_enable = uart_stm32_irq_err_enable,
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.irq_err_disable = uart_stm32_irq_err_disable,
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.irq_is_pending = uart_stm32_irq_is_pending,
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.irq_update = uart_stm32_irq_update,
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.irq_callback_set = uart_stm32_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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2016-03-03 15:33:20 +01:00
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};
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/**
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* @brief Initialize UART channel
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*
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* This routine is called to reset the chip in a quiescent state.
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* It is assumed that this function is called only once per UART.
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*
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* @param dev UART device struct
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*
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* @return 0
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*/
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static int uart_stm32_init(struct device *dev)
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{
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2016-11-14 11:53:52 +01:00
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const struct uart_stm32_config *config = DEV_CFG(dev);
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2016-03-03 15:33:20 +01:00
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struct uart_stm32_data *data = DEV_DATA(dev);
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2017-09-21 15:20:53 +02:00
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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u32_t clock_rate;
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2016-03-03 15:33:20 +01:00
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__uart_stm32_get_clock(dev);
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/* enable clock */
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2016-11-14 11:53:52 +01:00
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clock_control_on(data->clock,
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(clock_control_subsys_t *)&config->pclken);
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2016-03-03 15:33:20 +01:00
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2017-09-21 15:20:53 +02:00
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LL_USART_Disable(UartInstance);
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/* TX/RX direction */
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LL_USART_SetTransferDirection(UartInstance,
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LL_USART_DIRECTION_TX_RX);
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/* 8 data bit, 1 start bit, 1 stop bit, no parity */
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LL_USART_ConfigCharacter(UartInstance,
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LL_USART_DATAWIDTH_8B,
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LL_USART_PARITY_NONE,
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LL_USART_STOPBITS_1);
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/* Get clock rate */
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clock_control_get_rate(data->clock,
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(clock_control_subsys_t *)&config->pclken,
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&clock_rate);
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LL_USART_SetBaudRate(UartInstance,
|
|
|
|
clock_rate,
|
2017-12-13 09:23:57 -08:00
|
|
|
#ifdef USART_PRESC_PRESCALER
|
|
|
|
LL_USART_PRESCALER_DIV1,
|
|
|
|
#endif
|
2017-09-21 15:20:53 +02:00
|
|
|
#ifdef USART_CR1_OVER8
|
|
|
|
LL_USART_OVERSAMPLING_16,
|
|
|
|
#endif
|
2018-04-11 15:21:16 +03:00
|
|
|
config->baud_rate);
|
2017-09-21 15:20:53 +02:00
|
|
|
|
|
|
|
LL_USART_Enable(UartInstance);
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2017-09-21 15:20:53 +02:00
|
|
|
#if !defined(CONFIG_SOC_SERIES_STM32F4X) && !defined(CONFIG_SOC_SERIES_STM32F1X)
|
|
|
|
/* Polling USART initialisation */
|
|
|
|
while ((!(LL_USART_IsActiveFlag_TEACK(UartInstance))) ||
|
|
|
|
(!(LL_USART_IsActiveFlag_REACK(UartInstance))))
|
|
|
|
;
|
|
|
|
#endif /* !CONFIG_SOC_SERIES_STM32F4X */
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2016-03-13 19:37:25 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2016-11-14 11:53:52 +01:00
|
|
|
config->uconf.irq_config_func(dev);
|
2016-03-13 19:37:25 +01:00
|
|
|
#endif
|
2016-03-03 15:33:20 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-01 15:21:52 +02:00
|
|
|
/* Define clocks */
|
2018-04-11 16:19:13 +03:00
|
|
|
#define STM32_CLOCK_UART(clock_bus, clock_enr) \
|
|
|
|
.pclken = { .bus = clock_bus, \
|
|
|
|
.enr = clock_enr }
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2016-03-13 19:37:25 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2018-04-11 16:19:13 +03:00
|
|
|
#define STM32_UART_IRQ_HANDLER_DECL(name) \
|
|
|
|
static void uart_stm32_irq_config_func_##name(struct device *dev)
|
|
|
|
#define STM32_UART_IRQ_HANDLER_FUNC(name) \
|
|
|
|
.irq_config_func = uart_stm32_irq_config_func_##name,
|
|
|
|
#define STM32_UART_IRQ_HANDLER(name) \
|
|
|
|
static void uart_stm32_irq_config_func_##name(struct device *dev) \
|
2017-05-01 15:21:52 +02:00
|
|
|
{ \
|
2018-04-11 16:19:13 +03:00
|
|
|
IRQ_CONNECT(name##_IRQ, \
|
|
|
|
CONFIG_UART_STM32_##name##_IRQ_PRI, \
|
|
|
|
uart_stm32_isr, DEVICE_GET(uart_stm32_##name), \
|
2017-05-01 15:21:52 +02:00
|
|
|
0); \
|
2018-04-11 16:19:13 +03:00
|
|
|
irq_enable(name##_IRQ); \
|
2016-03-13 19:37:25 +01:00
|
|
|
}
|
2017-01-23 17:55:57 +01:00
|
|
|
#else
|
2018-04-11 16:19:13 +03:00
|
|
|
#define STM32_UART_IRQ_HANDLER_DECL(name)
|
|
|
|
#define STM32_UART_IRQ_HANDLER_FUNC(name)
|
|
|
|
#define STM32_UART_IRQ_HANDLER(name)
|
2017-05-01 15:21:52 +02:00
|
|
|
#endif
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2018-04-11 16:19:13 +03:00
|
|
|
#define STM32_UART_INIT(name, clock_bus, clock_enr) \
|
|
|
|
STM32_UART_IRQ_HANDLER_DECL(name); \
|
2017-05-01 15:21:52 +02:00
|
|
|
\
|
2018-04-11 16:19:13 +03:00
|
|
|
static const struct uart_stm32_config uart_stm32_cfg_##name = { \
|
2017-05-01 15:21:52 +02:00
|
|
|
.uconf = { \
|
2018-04-11 16:19:13 +03:00
|
|
|
.base = (u8_t *)CONFIG_UART_STM32_##name##_BASE_ADDRESS,\
|
|
|
|
STM32_UART_IRQ_HANDLER_FUNC(name) \
|
2017-05-01 15:21:52 +02:00
|
|
|
}, \
|
2017-12-18 11:33:48 +01:00
|
|
|
STM32_CLOCK_UART(clock_bus, clock_enr), \
|
2018-04-11 16:19:13 +03:00
|
|
|
.baud_rate = CONFIG_UART_STM32_##name##_BAUD_RATE \
|
2017-05-01 15:21:52 +02:00
|
|
|
}; \
|
|
|
|
\
|
2018-04-11 16:19:13 +03:00
|
|
|
static struct uart_stm32_data uart_stm32_data_##name = { \
|
2017-05-01 15:21:52 +02:00
|
|
|
}; \
|
|
|
|
\
|
2018-04-11 16:19:13 +03:00
|
|
|
DEVICE_AND_API_INIT(uart_stm32_##name, CONFIG_UART_STM32_##name##_NAME, \
|
2017-05-01 15:21:52 +02:00
|
|
|
&uart_stm32_init, \
|
2018-04-11 16:19:13 +03:00
|
|
|
&uart_stm32_data_##name, &uart_stm32_cfg_##name, \
|
2017-05-01 15:21:52 +02:00
|
|
|
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
|
|
&uart_stm32_driver_api); \
|
|
|
|
\
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_IRQ_HANDLER(name)
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2018-03-20 20:50:57 +03:00
|
|
|
/*
|
|
|
|
* STM32F0 and STM32L0 series differ from other STM32 series by some
|
|
|
|
* peripheral names (UART vs USART). Besides, STM32F0 doesn't have APB2 bus,
|
|
|
|
* so APB1 GRP2 should be accessed instead.
|
2017-12-18 11:38:10 +01:00
|
|
|
*/
|
2018-03-20 20:50:57 +03:00
|
|
|
#if defined(CONFIG_SOC_SERIES_STM32F0X)
|
|
|
|
|
2017-12-18 11:38:10 +01:00
|
|
|
#ifdef CONFIG_UART_STM32_PORT_1
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_1, STM32_CLOCK_BUS_APB1_2, LL_APB1_GRP2_PERIPH_USART1)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_1 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_2
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_2, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART2)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_2 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_3
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_3, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART3)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_3 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_4
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_4, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART4)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_4 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_5
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_5, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART5)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_5 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_6
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_6, STM32_CLOCK_BUS_APB1_2, LL_APB1_GRP2_PERIPH_USART6)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_6 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_7
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_7, STM32_CLOCK_BUS_APB1_2, LL_APB1_GRP2_PERIPH_USART7)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_7 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_8
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_8, STM32_CLOCK_BUS_APB1_2, LL_APB1_GRP2_PERIPH_USART8)
|
2017-12-18 11:38:10 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_8 */
|
|
|
|
|
2018-03-20 20:50:57 +03:00
|
|
|
#elif defined(CONFIG_SOC_SERIES_STM32L0X)
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_1
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_1, STM32_CLOCK_BUS_APB2, LL_APB2_GRP1_PERIPH_USART1)
|
2018-03-20 20:50:57 +03:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_1 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_2
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_2, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART2)
|
2018-03-20 20:50:57 +03:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_2 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_4
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_4, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART4)
|
2018-03-20 20:50:57 +03:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_4 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_5
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_5, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART5)
|
2018-03-20 20:50:57 +03:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_5 */
|
|
|
|
|
|
|
|
#else
|
2017-12-18 11:38:10 +01:00
|
|
|
|
2017-05-01 15:21:52 +02:00
|
|
|
#ifdef CONFIG_UART_STM32_PORT_1
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_1, STM32_CLOCK_BUS_APB2, LL_APB2_GRP1_PERIPH_USART1)
|
2017-05-01 15:21:52 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_1 */
|
2016-03-13 19:37:25 +01:00
|
|
|
|
2017-05-01 15:21:52 +02:00
|
|
|
#ifdef CONFIG_UART_STM32_PORT_2
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_2, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART2)
|
2016-11-14 11:59:45 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_2 */
|
2016-03-03 15:33:20 +01:00
|
|
|
|
2016-11-14 11:59:45 +01:00
|
|
|
#ifdef CONFIG_UART_STM32_PORT_3
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_3, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_USART3)
|
2016-11-14 11:59:45 +01:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_3 */
|
2017-05-01 15:22:02 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_4
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(UART_4, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_UART4)
|
2017-05-01 15:22:02 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_4 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_5
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(UART_5, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_UART5)
|
2017-05-01 15:22:02 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_5 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_6
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(USART_6, STM32_CLOCK_BUS_APB2, LL_APB2_GRP1_PERIPH_USART6)
|
2017-05-01 15:22:02 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_6 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_7
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(UART_7, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_UART7)
|
2017-05-01 15:22:02 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_7 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_8
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(UART_8, STM32_CLOCK_BUS_APB1, LL_APB1_GRP1_PERIPH_UART8)
|
2017-05-01 15:22:02 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_8 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_9
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(UART_9, STM32_CLOCK_BUS_APB2, LL_APB2_GRP1_PERIPH_UART9)
|
2017-05-01 15:22:02 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_9 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_STM32_PORT_10
|
2018-04-11 16:19:13 +03:00
|
|
|
STM32_UART_INIT(UART_10, STM32_CLOCK_BUS_APB2, LL_APB2_GRP1_PERIPH_UART10)
|
2017-05-01 15:22:02 +02:00
|
|
|
#endif /* CONFIG_UART_STM32_PORT_10 */
|
2018-03-20 20:50:57 +03:00
|
|
|
|
|
|
|
#endif
|