2017-08-09 11:21:09 +02:00
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/*
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* Copyright (c) 2017 RnDity Sp. z o.o.
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2019-07-15 15:36:31 +03:00
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* Copyright (c) 2019 Centaur Analytics, Inc
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2017-08-09 11:21:09 +02:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv6-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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2017-11-30 10:59:53 +01:00
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#include <dt-bindings/i2c/i2c.h>
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2017-11-27 09:33:17 +01:00
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#include <dt-bindings/gpio/gpio.h>
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2020-04-23 16:10:12 +02:00
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#include <dt-bindings/pwm/pwm.h>
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2017-08-09 11:21:09 +02:00
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/ {
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2020-04-22 13:46:15 -05:00
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chosen {
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zephyr,flash-controller = &flash;
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};
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2017-08-09 11:21:09 +02:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0";
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reg = <0>;
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};
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};
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2017-12-04 14:09:14 +01:00
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2017-08-09 11:21:09 +02:00
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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2020-04-22 13:46:15 -05:00
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flash: flash-controller@40022000 {
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2020-04-13 18:00:09 +02:00
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compatible = "st,stm32-flash-controller", "st,stm32f0-flash-controller";
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2018-01-23 12:52:50 -06:00
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label = "FLASH_CTRL";
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reg = <0x40022000 0x400>;
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interrupts = <3 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <2>;
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};
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};
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2017-08-09 11:21:09 +02:00
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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2018-04-23 17:48:37 +02:00
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#clock-cells = <2>;
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2017-08-09 11:21:09 +02:00
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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2018-04-24 15:32:10 +02:00
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pinctrl: pin-controller@48000000 {
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2017-08-09 11:21:09 +02:00
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compatible = "st,stm32-pinmux";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x48000000 0x1800>;
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2017-11-23 11:31:59 +01:00
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gpioa: gpio@48000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000000 0x400>;
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2018-12-06 16:03:41 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
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2017-11-23 11:31:59 +01:00
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label = "GPIOA";
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};
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gpiob: gpio@48000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000400 0x400>;
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2018-12-06 16:03:41 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
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2017-11-23 11:31:59 +01:00
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label = "GPIOB";
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};
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gpioc: gpio@48000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000800 0x400>;
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2018-12-06 16:03:41 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
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2017-11-23 11:31:59 +01:00
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label = "GPIOC";
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};
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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2018-12-06 16:03:41 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
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2017-11-23 11:31:59 +01:00
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label = "GPIOD";
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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2018-12-06 16:03:41 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
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2017-11-23 11:31:59 +01:00
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label = "GPIOF";
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};
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2017-08-09 11:21:09 +02:00
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
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interrupts = <27 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <28 0>;
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status = "disabled";
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label = "UART_2";
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};
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2017-11-30 10:59:53 +01:00
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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2018-07-05 19:51:10 +03:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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2017-11-30 10:59:53 +01:00
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interrupts = <23 0>;
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interrupt-names = "combined";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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2018-07-03 17:00:40 +02:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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2017-11-30 10:59:53 +01:00
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interrupts = <24 0>;
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interrupt-names = "combined";
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status = "disabled";
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label= "I2C_2";
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};
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2018-01-05 19:51:35 +02:00
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spi1: spi@40013000 {
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drivers/spi: stm32: Modify use of "st,stm32-spi-fifo" compatible
On stm32 spi devices, there are 2 main IP variants, with and w/o
fifo. Fifo is not really used today, but still there is some
additional code handling fifo. Today this code is protected under
Kconfig symbol SPI_STM32_HAS_FIFO.
This code carries redundant information vs dedicated compatible
"st,stm32-spi-fifo", which is provided as unique driver compatible
for devices supporting this IP as opposed to use of "st,stm32-spi"
when fifo is not supported.
Having these 2 compatibles defined exclusively is not convenient for
migration to DT_INST as DT_INST macros contain compatible string and
hence it cannot be used to provide common compatible code for devices
defining different compatibles.
Based on these observations, review stm32 spi devices compatible
declarations. Devices supporting fifo will now declare both
compatibles, as proposed by dt spec: "[compatible] property value
consists of a concatenated list of null terminated strings,
from most specific to most general". Hence field will now be:
"st,stm32-spi-fifo", "st,stm32-spi"
This way, fifo enabled stm32 spi devices will generate both:
DT_INST_STM32_SPI_FOO and DT_INST_STM32_SPI_FIFO_FOO
As well as:
DT_COMPAT_ST_STM32_SPI and DT_COMPAT_ST_STM32_SPI_FIFO
So, DT_INST_STM32_SPI_FOO could be used for device initialization.
Also DT_COMPAT_ST_STM32_SPI_FIFO could be used for FIFO handling
code inside driver. Hence use it to replace Kconfig symbol
SPI_STM32_HAS_FIFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-09 10:43:41 +01:00
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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2018-01-05 19:51:35 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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2019-11-05 17:21:58 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
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2018-02-17 16:57:20 +02:00
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interrupts = <25 3>;
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2018-01-05 19:51:35 +02:00
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status = "disabled";
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label = "SPI_1";
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};
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2018-02-28 22:15:00 +01:00
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2019-04-04 15:46:31 +08:00
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iwdg: watchdog@40003000 {
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2019-02-01 14:50:46 +01:00
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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label = "IWDG";
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};
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2019-07-15 15:36:31 +03:00
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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label = "WWDG";
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interrupts = <0 7>;
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status = "disabled";
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};
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2018-02-28 22:15:00 +01:00
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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2019-11-05 17:21:58 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
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2018-02-28 22:15:00 +01:00
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status = "disabled";
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label = "TIMERS_1";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_1";
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2020-04-23 16:10:12 +02:00
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#pwm-cells = <3>;
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2018-02-28 22:15:00 +01:00
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_3";
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2020-04-23 16:10:12 +02:00
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#pwm-cells = <3>;
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2018-02-28 22:15:00 +01:00
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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status = "disabled";
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label = "TIMERS_6";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_6";
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2020-04-23 16:10:12 +02:00
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#pwm-cells = <3>;
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2018-02-28 22:15:00 +01:00
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};
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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status = "disabled";
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label = "TIMERS_7";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_7";
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2020-04-23 16:10:12 +02:00
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#pwm-cells = <3>;
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2018-02-28 22:15:00 +01:00
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};
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};
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timers14: timers@40002000 {
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
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status = "disabled";
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label = "TIMERS_14";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_14";
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2020-04-23 16:10:12 +02:00
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#pwm-cells = <3>;
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2018-02-28 22:15:00 +01:00
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};
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};
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timers15: timers@40014000 {
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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2019-11-05 17:21:58 +01:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
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2018-02-28 22:15:00 +01:00
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status = "disabled";
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label = "TIMERS_15";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_15";
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2020-04-23 16:10:12 +02:00
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#pwm-cells = <3>;
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2018-02-28 22:15:00 +01:00
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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2019-11-05 17:21:58 +01:00
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
|
2018-02-28 22:15:00 +01:00
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_16";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_16";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2018-02-28 22:15:00 +01:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers17: timers@40014800 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40014800 0x400>;
|
2019-11-05 17:21:58 +01:00
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
|
2018-02-28 22:15:00 +01:00
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_17";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_17";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2018-02-28 22:15:00 +01:00
|
|
|
};
|
|
|
|
|
};
|
2019-05-07 16:36:30 +08:00
|
|
|
|
|
|
|
|
adc1: adc@40012400 {
|
|
|
|
|
compatible = "st,stm32-adc";
|
|
|
|
|
reg = <0x40012400 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
|
|
|
|
|
interrupts = <12 0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "ADC_1";
|
2019-08-22 11:08:13 -05:00
|
|
|
#io-channel-cells = <1>;
|
2019-05-07 16:36:30 +08:00
|
|
|
};
|
2019-10-24 12:34:28 +08:00
|
|
|
|
|
|
|
|
dma1: dma@40020000 {
|
|
|
|
|
compatible = "st,stm32-dma";
|
|
|
|
|
#dma-cells = <4>;
|
|
|
|
|
reg = <0x40020000 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
|
|
|
|
|
interrupts = <9 0 10 0 10 0 11 0 11 0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "DMA_1";
|
|
|
|
|
};
|
2017-08-09 11:21:09 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&nvic {
|
|
|
|
|
arm,num-irq-priority-bits = <2>;
|
|
|
|
|
};
|
