zephyr/soc/arm/nxp_s32/s32k3/Kconfig.series

# NXP S32K3XX MCU series

# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_S32K3XX
	bool "NXP S32K3XX MCU series"
	select ARM
	select CPU_CORTEX_M7
	select SOC_FAMILY_NXP_S32
	select HAS_NXP_S32_HAL
	select CPU_HAS_FPU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
	select PLATFORM_SPECIFIC_INIT if XIP
	select USE_DT_CODE_PARTITION if XIP
	select CLOCK_CONTROL
	select HAS_MCUX
	select HAS_MCUX_LPUART
	select HAS_MCUX_FLEXCAN
	select HAS_MCUX_LPI2C
	select HAS_MCUX_LPSPI
	select HAS_MCUX_CACHE
	help
	  Enable support for NXP S32K3XX MCU series.
soc: nxp_s32: s32k3: drop `M7` suffix from options The existing S32K3 Kconfig options employ the `M7` suffix, which is redundant given that all cores in this series utilize an Arm Cortex-M7 core. Therefore, we should remove it. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-11-06 22:49:27 +07:00			`# NXP S32K3XX MCU series`
soc: arm: introduce support for NXP S32K344 The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a focus on automotive and industrial applications. The S32K344 features a lock-step core, internal flash, RAM and TCM with ECC. Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com> Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-05-26 00:00:00 +00:00
			`# Copyright 2023 NXP`
			`# SPDX-License-Identifier: Apache-2.0`

soc: nxp_s32: s32k3: drop `M7` suffix from options The existing S32K3 Kconfig options employ the `M7` suffix, which is redundant given that all cores in this series utilize an Arm Cortex-M7 core. Therefore, we should remove it. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-11-06 22:49:27 +07:00			`config SOC_SERIES_S32K3XX`
			`bool "NXP S32K3XX MCU series"`
soc: arm: introduce support for NXP S32K344 The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a focus on automotive and industrial applications. The S32K344 features a lock-step core, internal flash, RAM and TCM with ECC. Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com> Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-05-26 00:00:00 +00:00			`select ARM`
			`select CPU_CORTEX_M7`
soc: nxp_s32: rename family to SOC_FAMILY_NXP_S32 Rename NXP S32 device's family to SOC_FAMILY_NXP_S32 to avoid ambiguity. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-08-06 12:54:25 +07:00			`select SOC_FAMILY_NXP_S32`
soc: nxp_s32: s32k3: drop `M7` suffix from options The existing S32K3 Kconfig options employ the `M7` suffix, which is redundant given that all cores in this series utilize an Arm Cortex-M7 core. Therefore, we should remove it. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-11-06 22:49:27 +07:00			`select HAS_NXP_S32_HAL`
soc: arm: introduce support for NXP S32K344 The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a focus on automotive and industrial applications. The S32K344 features a lock-step core, internal flash, RAM and TCM with ECC. Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com> Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-05-26 00:00:00 +00:00			`select CPU_HAS_FPU`
			`select CPU_HAS_ARM_MPU`
arch: arm: cortex_m: Remove CPU_HAS_CACHE from CPU_CORTEX_M7 Caches are optional on cortex-m7, having CPU_HAS_CACHE in CPU_CORTEX_M7 definition renders them mandatory. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com> 2023-11-05 04:09:36 +00:00			`select CPU_HAS_ICACHE`
			`select CPU_HAS_DCACHE`
soc: arm: introduce support for NXP S32K344 The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a focus on automotive and industrial applications. The S32K344 features a lock-step core, internal flash, RAM and TCM with ECC. Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com> Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-05-26 00:00:00 +00:00			`select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS`
			`select PLATFORM_SPECIFIC_INIT if XIP`
			`select USE_DT_CODE_PARTITION if XIP`
soc: nxp: s32k3: enable clock control Enable clock control by default on S32K344 SoCs and add clock definitions. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-05-26 00:00:00 +00:00			`select CLOCK_CONTROL`
boards: mr_canhubk3: enable LPUART serial driver Reuse existing MCUX-based shim driver for LPUART that is compatible with the hardware block in S32K344. DMA is not yet supported. Use the board's debug connector (P6 / LPUART2) as default console. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-05-26 00:00:00 +00:00			`select HAS_MCUX`
			`select HAS_MCUX_LPUART`
boards: arm: mr_canhubk3: enable support for FlexCAN Reuse existing MCUX-based shim driver for FlexCAN. Enable flexcan0 for Zephyr canbus to run tests. Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com> 2023-06-14 14:20:41 +07:00			`select HAS_MCUX_FLEXCAN`
drivers: i2c_mcux: update to compatible with S32K344 Update to shim driver compatible with the hardware block in S32K344. Configure the pins before initializing I2C to avoid happening bus busy. Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com> 2023-07-10 13:37:46 +07:00			`select HAS_MCUX_LPI2C`
soc: nxp_s32: add LPSPI to S32K344 Reuse existing NXP LPSPI binding for this SoC since the hardware block for this device is the same as the one supported for other NXP devices. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-07-06 17:49:58 -03:00			`select HAS_MCUX_LPSPI`
drivers: dma_mcux_edma: add support dma driver for s32k344 On S32K344, the offset in memory map between each channel is 0x4000 for most channels, but there is specific case is between channel 11 and 12 which is 0x1D4000 instead. As a consequence, 32 channels are divided to two parts: one starts from channel 0 -> 11. The other is from channel 128 to 145. The channel gap is from 12 -> 127. For user and data structures in shim driver, the channel's value comes from 0 --> 31. Above constraint will be counted when interact with the mcux sdk Beside that, the DMAMUX register in this platform is very specific, not in identical with DMAMUX channel, so shim driver is updated to cover this case Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> 2023-06-14 10:23:06 +07:00			`select HAS_MCUX_CACHE`
soc: arm: introduce support for NXP S32K344 The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a focus on automotive and industrial applications. The S32K344 features a lock-step core, internal flash, RAM and TCM with ECC. Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com> Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-05-26 00:00:00 +00:00			`help`
soc: nxp_s32: s32k3: drop `M7` suffix from options The existing S32K3 Kconfig options employ the `M7` suffix, which is redundant given that all cores in this series utilize an Arm Cortex-M7 core. Therefore, we should remove it. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> 2023-11-06 22:49:27 +07:00			`Enable support for NXP S32K3XX MCU series.`