2019-11-01 13:45:29 +01:00
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# x86 general configuration options
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2015-05-20 18:40:39 +02:00
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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2017-01-19 02:01:01 +01:00
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# SPDX-License-Identifier: Apache-2.0
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2019-06-25 18:36:17 +02:00
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2017-09-09 03:14:06 +02:00
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menu "X86 Architecture Options"
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2015-10-09 12:20:52 +02:00
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depends on X86
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2015-05-26 16:31:43 +02:00
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2015-10-09 12:20:52 +02:00
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config ARCH
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2016-05-25 01:17:13 +02:00
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default "x86"
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2015-05-26 16:31:43 +02:00
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2016-03-15 17:02:42 +01:00
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#
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2019-06-12 23:03:45 +02:00
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# CPU Families - the SoC configuration should select the right one.
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2016-03-15 17:02:42 +01:00
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#
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2019-06-12 23:03:45 +02:00
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2015-06-11 23:05:13 +02:00
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config CPU_ATOM
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2019-12-23 12:07:30 +01:00
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bool
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2016-03-15 17:24:49 +01:00
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select CPU_HAS_FPU
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2019-11-05 23:00:30 +01:00
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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2019-12-19 08:57:25 +01:00
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select ARCH_HAS_USERSPACE if X86_MMU
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2021-01-08 01:13:52 +01:00
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_CPU_HAS_SSE3
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2022-07-25 10:43:24 +02:00
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select CPU_HAS_DCACHE
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2015-06-11 23:05:13 +02:00
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help
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2017-12-13 16:08:21 +01:00
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This option signifies the use of a CPU from the Atom family.
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2015-06-11 23:05:13 +02:00
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2018-07-17 03:37:14 +02:00
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config CPU_APOLLO_LAKE
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2019-12-23 12:07:30 +01:00
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bool
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2018-07-17 03:37:14 +02:00
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select CPU_HAS_FPU
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2019-11-05 23:00:30 +01:00
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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2019-12-19 08:57:25 +01:00
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select ARCH_HAS_USERSPACE if X86_MMU
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2021-01-08 01:13:52 +01:00
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select X86_MMU
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_CPU_HAS_SSE3
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select X86_CPU_HAS_SSSE3
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select X86_CPU_HAS_SSE41
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select X86_CPU_HAS_SSE42
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2022-07-25 10:43:24 +02:00
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select CPU_HAS_DCACHE
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2018-07-17 03:37:14 +02:00
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help
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This option signifies the use of a CPU from the Apollo Lake family.
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2021-02-08 23:25:47 +01:00
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config CPU_LAKEMONT
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bool
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_CPU_HAS_SSE3
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select X86_CPU_HAS_SSSE3
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2022-07-25 10:43:24 +02:00
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select CPU_HAS_DCACHE
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2021-02-08 23:25:47 +01:00
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help
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This option signifies the use of a CPU from the Lakemont family.
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2019-06-12 23:03:45 +02:00
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#
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2019-06-25 18:36:17 +02:00
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# Configuration common to both IA32 and Intel64 sub-architectures.
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2019-06-12 23:03:45 +02:00
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#
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2019-03-02 22:15:16 +01:00
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2019-10-24 21:57:57 +02:00
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config X86_64
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2019-12-02 16:57:17 +01:00
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bool "Run in 64-bit mode"
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2019-07-23 19:13:38 +02:00
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select 64BIT
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2019-09-23 19:57:12 +02:00
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select USE_SWITCH
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2019-09-30 19:28:36 +02:00
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select USE_SWITCH_SUPPORTED
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select SCHED_IPI_SUPPORTED
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2020-07-05 01:23:32 +02:00
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select X86_MMU
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2021-01-08 01:13:52 +01:00
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_MMX
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select X86_SSE
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select X86_SSE2
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2019-03-02 22:15:16 +01:00
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2021-01-08 00:07:29 +01:00
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menu "x86 Features"
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2021-01-08 01:13:52 +01:00
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config X86_CPU_HAS_MMX
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bool
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config X86_CPU_HAS_SSE
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bool
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config X86_CPU_HAS_SSE2
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bool
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config X86_CPU_HAS_SSE3
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bool
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config X86_CPU_HAS_SSSE3
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bool
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config X86_CPU_HAS_SSE41
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bool
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config X86_CPU_HAS_SSE42
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bool
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config X86_CPU_HAS_SSE4A
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bool
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if FPU || X86_64
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config X86_MMX
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2022-03-09 12:05:12 +01:00
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bool "MMX Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_MMX
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help
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This option enables MMX support, and the use of MMX registers
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by threads.
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2021-01-08 00:07:29 +01:00
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config X86_SSE
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2022-03-09 12:05:12 +01:00
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bool "SSE Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_SSE
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2021-01-08 00:07:29 +01:00
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help
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This option enables SSE support, and the use of SSE registers
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by threads.
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2021-01-08 01:13:52 +01:00
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config X86_SSE2
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2022-03-09 12:05:12 +01:00
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bool "SSE2 Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_SSE2
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select X86_SSE
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help
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This option enables SSE2 support.
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config X86_SSE3
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2022-03-09 12:05:12 +01:00
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bool "SSE3 Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_SSE3
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select X86_SSE
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help
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This option enables SSE3 support.
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config X86_SSSE3
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2022-03-09 12:05:12 +01:00
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bool "SSSE3 (Supplemental SSE3) Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_SSSE3
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select X86_SSE
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help
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This option enables Supplemental SSE3 support.
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config X86_SSE41
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2022-03-09 12:05:12 +01:00
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bool "SSE4.1 Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_SSE41
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select X86_SSE
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help
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This option enables SSE4.1 support.
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config X86_SSE42
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2022-03-09 12:05:12 +01:00
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bool "SSE4.2 Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_SSE42
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select X86_SSE
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help
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This option enables SSE4.2 support.
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config X86_SSE4A
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2022-03-09 12:05:12 +01:00
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bool "SSE4A Support"
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2021-01-08 01:13:52 +01:00
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depends on X86_CPU_HAS_SSE4A
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select X86_SSE
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help
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This option enables SSE4A support.
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2021-01-08 00:07:29 +01:00
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config X86_SSE_FP_MATH
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bool "Compiler-generated SSEx instructions for floating point math"
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depends on X86_SSE
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help
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This option allows the compiler to generate SSEx instructions for
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performing floating point math. This can greatly improve performance
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when exactly the same operations are to be performed on multiple
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data objects; however, it can also significantly reduce performance
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when preemptive task switches occur because of the larger register
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set that must be saved and restored.
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Disabling this option means that the compiler utilizes only the
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x87 instruction set for floating point operations.
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2021-01-08 01:13:52 +01:00
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endif # FPU || X86_64
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2021-01-08 00:07:29 +01:00
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endmenu
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2021-02-20 20:11:24 +01:00
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config SRAM_OFFSET
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default 0x100000 if X86_PC_COMPATIBLE
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2020-06-17 21:20:17 +02:00
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help
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A lot of x86 that resemble PCs have many reserved physical memory
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regions within the first megabyte. Specify an offset from the
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beginning of RAM to load the kernel in physical memory, avoiding these
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regions.
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Note that this does not include the "locore" which contains real mode
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bootstrap code within the first 64K of physical memory.
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This value normally need to be page-aligned.
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2021-02-20 20:11:24 +01:00
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config KERNEL_VM_OFFSET
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default 0x100000 if MMU
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2019-07-05 05:17:14 +02:00
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config MAX_IRQ_LINES
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int "Number of IRQ lines"
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default 128
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2019-09-30 17:51:49 +02:00
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range 0 224
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2019-07-05 05:17:14 +02:00
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help
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This option specifies the number of IRQ lines in the system. It
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determines the size of the _irq_to_interrupt_vector_table, which
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is used to track the association between vectors and IRQ numbers.
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2019-07-10 02:34:52 +02:00
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config IRQ_OFFLOAD_VECTOR
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int "IDT vector to use for IRQ offload"
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2019-12-18 23:12:54 +01:00
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default 33
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2019-07-10 02:34:52 +02:00
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range 32 255
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depends on IRQ_OFFLOAD
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2019-06-12 23:03:45 +02:00
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config PIC_DISABLE
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bool "Disable PIC"
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2019-03-02 22:15:16 +01:00
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help
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2019-06-12 23:03:45 +02:00
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This option disables all interrupts on the legacy i8259 PICs at boot.
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2015-06-10 16:25:07 +02:00
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2016-01-18 23:36:00 +01:00
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choice
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2019-06-12 23:03:45 +02:00
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prompt "Reboot implementation"
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depends on REBOOT
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default REBOOT_RST_CNT
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config REBOOT_RST_CNT
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bool "Reboot via RST_CNT register"
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help
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Reboot via the RST_CNT register, going back to BIOS.
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2016-01-18 23:36:00 +01:00
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endchoice
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2020-06-13 15:34:46 +02:00
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config PCIE_MMIO_CFG
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bool "Use MMIO PCI configuration space access"
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2023-07-02 11:57:24 +02:00
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select ACPI
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2020-06-13 15:34:46 +02:00
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help
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Selects the use of the memory-mapped PCI Express Extended
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Configuration Space instead of the traditional 0xCF8/0xCFC
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IO Port registers.
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2021-01-26 20:33:38 +01:00
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config KERNEL_VM_SIZE
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2023-07-02 11:57:24 +02:00
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default 0x40000000 if ACPI
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2021-01-26 20:33:38 +01:00
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2021-02-09 22:26:40 +01:00
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config X86_PC_COMPATIBLE
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bool
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default y
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select ARCH_HAS_RESERVED_PAGE_FRAMES
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2021-02-20 20:11:24 +01:00
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select HAS_SRAM_OFFSET
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2021-02-09 22:26:40 +01:00
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help
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Hidden option to signal building for PC-compatible platforms
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with BIOS, ACPI, etc.
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2021-02-09 22:42:46 +01:00
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config X86_MEMMAP
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bool "Use memory map"
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select ARCH_HAS_RESERVED_PAGE_FRAMES
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help
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Enable the use of memory map to identify regions of memory.
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The memory map can be populated via Multiboot
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(CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or
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can be manually defined via x86_memmap[].
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2019-09-10 21:18:47 +02:00
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config X86_MEMMAP_ENTRIES
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int "Number of memory map entries"
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2021-02-09 22:42:46 +01:00
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depends on X86_MEMMAP
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2019-09-10 21:18:47 +02:00
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range 1 256
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2019-09-27 20:53:40 +02:00
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default 1 if !MULTIBOOT_MEMMAP
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default 64 if MULTIBOOT_MEMMAP
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2019-09-10 21:18:47 +02:00
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help
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Maximum number of memory regions to hold in the memory map.
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2019-09-27 20:53:40 +02:00
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config MULTIBOOT
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2019-06-12 23:03:45 +02:00
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bool "Generate multiboot header"
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2021-02-09 22:26:40 +01:00
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depends on X86_PC_COMPATIBLE
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2015-09-18 22:36:57 +02:00
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default y
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2015-11-30 02:20:42 +01:00
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help
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2019-06-12 23:03:45 +02:00
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Embed a multiboot header in the output executable. This is used
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by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe
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to leave this option on if you're not sure. It only expands the
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text segment by 12-16 bytes and is typically ignored if not needed.
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2015-06-10 16:25:07 +02:00
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2019-09-27 20:53:40 +02:00
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if MULTIBOOT
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2019-09-10 21:18:47 +02:00
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2019-09-27 20:53:40 +02:00
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config MULTIBOOT_INFO
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2019-06-12 23:03:45 +02:00
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bool "Preserve multiboot information structure"
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2015-07-31 22:52:22 +02:00
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help
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2019-06-12 23:03:45 +02:00
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Multiboot passes a pointer to an information structure to the
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kernel entry point. Some drivers (e.g., the multiboot framebuffer
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display driver) need to refer to information in this structure,
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and so set this option to preserve the data in a permanent location.
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2015-07-31 22:52:22 +02:00
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2019-09-27 20:53:40 +02:00
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config MULTIBOOT_MEMMAP
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2019-09-10 21:18:47 +02:00
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bool "Use multiboot memory map if provided"
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2019-09-27 20:53:40 +02:00
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select MULTIBOOT_INFO
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2021-02-09 22:42:46 +01:00
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select X86_MEMMAP
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2019-09-10 21:18:47 +02:00
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help
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Use the multiboot memory map if the loader provides one.
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2015-12-09 19:18:30 +01:00
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2019-09-27 20:53:40 +02:00
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endif # MULTIBOOT
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2016-08-02 21:05:08 +02:00
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2019-08-01 22:04:53 +02:00
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config X86_VERY_EARLY_CONSOLE
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bool "Support very early boot printk"
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depends on PRINTK
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help
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Non-emulated X86 devices often require special hardware to attach
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a debugger, which may not be easily available. This option adds a
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very minimal serial driver which gets initialized at the very
|
2019-11-07 21:43:29 +01:00
|
|
|
beginning of z_cstart(), via arch_kernel_init(). This driver enables
|
2019-08-01 22:04:53 +02:00
|
|
|
printk to emit messages to the 16550 UART port 0 instance in device
|
|
|
|
tree. This mini-driver assumes I/O to the UART is done via ports.
|
|
|
|
|
2019-10-10 22:05:43 +02:00
|
|
|
config X86_MMU
|
2022-03-09 12:05:12 +01:00
|
|
|
bool "Memory Management Unit"
|
2020-07-08 21:19:02 +02:00
|
|
|
select MMU
|
2019-10-10 22:05:43 +02:00
|
|
|
help
|
|
|
|
This options enables the memory management unit present in x86
|
|
|
|
and creates a set of page tables at boot time that is runtime-
|
|
|
|
mutable.
|
|
|
|
|
2020-10-27 19:27:37 +01:00
|
|
|
config X86_COMMON_PAGE_TABLE
|
|
|
|
bool "Use a single page table for all threads"
|
|
|
|
default n
|
|
|
|
depends on USERSPACE
|
|
|
|
depends on !SMP
|
|
|
|
depends on !X86_KPTI
|
|
|
|
help
|
|
|
|
If this option is enabled, userspace memory domains will not have their
|
|
|
|
own page tables. Instead, context switching operations will modify
|
|
|
|
page tables in place. This is much slower, but uses much less RAM
|
|
|
|
for page tables.
|
|
|
|
|
2020-12-18 06:12:40 +01:00
|
|
|
config X86_MAX_ADDITIONAL_MEM_DOMAINS
|
|
|
|
int "Maximum number of memory domains"
|
|
|
|
default 3
|
|
|
|
depends on X86_MMU && USERSPACE && !X86_COMMON_PAGE_TABLE
|
|
|
|
help
|
|
|
|
The initial page tables at boot are pre-allocated, and used for the
|
|
|
|
default memory domain. Instantiation of additional memory domains
|
|
|
|
if common page tables are in use requires a pool of free pinned
|
|
|
|
memory pages for constructing page tables.
|
|
|
|
|
|
|
|
Zephyr test cases assume 3 additional domains can be instantiated.
|
|
|
|
|
2021-03-02 23:14:15 +01:00
|
|
|
config X86_EXTRA_PAGE_TABLE_PAGES
|
|
|
|
int "Reserve extra pages in page table"
|
2021-05-03 22:07:31 +02:00
|
|
|
default 1 if X86_PAE && (KERNEL_VM_BASE != SRAM_BASE_ADDRESS)
|
2021-03-02 23:14:15 +01:00
|
|
|
default 0
|
|
|
|
depends on X86_MMU
|
|
|
|
help
|
|
|
|
The whole page table is pre-allocated at build time and is
|
|
|
|
dependent on the range of address space. This allows reserving
|
|
|
|
extra pages (of size CONFIG_MMU_PAGE_SIZE) to the page table
|
|
|
|
so that gen_mmu.py can make use of these extra pages.
|
|
|
|
|
|
|
|
Says 0 unless absolutely sure that this is necessary.
|
|
|
|
|
2019-10-10 22:05:43 +02:00
|
|
|
config X86_NO_MELTDOWN
|
|
|
|
bool
|
|
|
|
help
|
|
|
|
This hidden option should be set on a per-SOC basis to indicate that
|
|
|
|
a particular SOC is not vulnerable to the Meltdown CPU vulnerability,
|
|
|
|
as described in CVE-2017-5754.
|
|
|
|
|
|
|
|
config X86_NO_SPECTRE_V1
|
|
|
|
bool
|
|
|
|
help
|
|
|
|
This hidden option should be set on a per-SOC basis to indicate that
|
2020-01-04 03:13:33 +01:00
|
|
|
a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and
|
|
|
|
swapgs CPU vulnerabilities as described in CVE-2017-5753,
|
|
|
|
CVE-2018-3693, and CVE-2019-1125.
|
2019-10-10 22:05:43 +02:00
|
|
|
|
|
|
|
config X86_NO_SPECTRE_V2
|
|
|
|
bool
|
|
|
|
help
|
|
|
|
This hidden option should be set on a per-SOC basis to indicate that
|
|
|
|
a particular SOC is not vulnerable to the Spectre V2 CPU
|
|
|
|
vulnerability, as described in CVE-2017-5715.
|
|
|
|
|
|
|
|
config X86_NO_SPECTRE_V4
|
|
|
|
bool
|
|
|
|
help
|
|
|
|
This hidden option should be set on a per-SOC basis to indicate that
|
|
|
|
a particular SOC is not vulnerable to the Spectre V4 CPU
|
|
|
|
vulnerability, as described in CVE-2018-3639.
|
|
|
|
|
|
|
|
config X86_NO_LAZY_FP
|
|
|
|
bool
|
|
|
|
help
|
|
|
|
This hidden option should be set on a per-SOC basis to indicate
|
|
|
|
that a particular SOC is not vulnerable to the Lazy FP CPU
|
|
|
|
vulnerability, as described in CVE-2018-3665.
|
|
|
|
|
|
|
|
config X86_NO_SPECULATIVE_VULNERABILITIES
|
|
|
|
bool
|
|
|
|
select X86_NO_MELTDOWN
|
|
|
|
select X86_NO_SPECTRE_V1
|
|
|
|
select X86_NO_SPECTRE_V2
|
|
|
|
select X86_NO_SPECTRE_V4
|
|
|
|
select X86_NO_LAZY_FP
|
|
|
|
help
|
|
|
|
This hidden option should be set on a per-SOC basis to indicate that
|
|
|
|
a particular SOC does not perform any kind of speculative execution,
|
|
|
|
or is a newer chip which is immune to the class of vulnerabilities
|
|
|
|
which exploit speculative execution side channel attacks.
|
|
|
|
|
2024-03-01 19:43:41 +01:00
|
|
|
config X86_DISABLE_SSBD
|
2019-11-20 08:28:17 +01:00
|
|
|
bool "Disable Speculative Store Bypass"
|
|
|
|
depends on USERSPACE
|
|
|
|
default y if !X86_NO_SPECTRE_V4
|
|
|
|
help
|
|
|
|
This option will disable Speculative Store Bypass in order to
|
|
|
|
mitigate against certain kinds of side channel attacks. Quoting
|
|
|
|
the "Speculative Execution Side Channels" document, version 2.0:
|
|
|
|
|
|
|
|
When SSBD is set, loads will not execute speculatively
|
|
|
|
until the addresses of all older stores are known. This
|
|
|
|
ensure s that a load does not speculatively consume stale
|
|
|
|
data values due to bypassing an older store on the same
|
|
|
|
logical processor.
|
|
|
|
|
|
|
|
If enabled, this applies to all threads in the system.
|
|
|
|
|
|
|
|
Even if enabled, will have no effect on CPUs that do not
|
|
|
|
require this feature.
|
|
|
|
|
2024-03-01 19:43:41 +01:00
|
|
|
config DISABLE_SSBD
|
|
|
|
bool "Disable Speculative Store Bypass [DEPRECATED]"
|
|
|
|
depends on USERSPACE
|
|
|
|
default y if !X86_NO_SPECTRE_V4
|
|
|
|
select X86_DISABLE_SSBD
|
|
|
|
select DEPRECATED
|
|
|
|
help
|
|
|
|
Deprecated. Use CONFIG_X86_DISABLE_SSBD instead.
|
|
|
|
|
|
|
|
config X86_ENABLE_EXTENDED_IBRS
|
2022-03-09 12:05:12 +01:00
|
|
|
bool "Extended IBRS"
|
2019-11-20 08:28:17 +01:00
|
|
|
depends on USERSPACE
|
|
|
|
default y if !X86_NO_SPECTRE_V2
|
|
|
|
help
|
|
|
|
This option will enable the Extended Indirect Branch Restricted
|
|
|
|
Speculation 'always on' feature. This mitigates Indirect Branch
|
|
|
|
Control vulnerabilities (aka Spectre V2).
|
|
|
|
|
2024-03-01 19:43:41 +01:00
|
|
|
config ENABLE_EXTENDED_IBRS
|
|
|
|
bool "Extended IBRS [DEPRECATED]"
|
|
|
|
depends on USERSPACE
|
|
|
|
default y if !X86_NO_SPECTRE_V2
|
|
|
|
select X86_ENABLE_EXTENDED_IBRS
|
|
|
|
select DEPRECATED
|
|
|
|
help
|
|
|
|
Deprecated. Use CONFIG_X86_ENABLE_EXTENDED_IBRS instead.
|
|
|
|
|
2019-11-20 08:28:17 +01:00
|
|
|
config X86_BOUNDS_CHECK_BYPASS_MITIGATION
|
|
|
|
bool
|
|
|
|
depends on USERSPACE
|
|
|
|
default y if !X86_NO_SPECTRE_V1
|
|
|
|
select BOUNDS_CHECK_BYPASS_MITIGATION
|
|
|
|
help
|
|
|
|
Hidden config to select arch-independent option to enable
|
|
|
|
Spectre V1 mitigations by default if the CPU is not known
|
|
|
|
to be immune to it.
|
|
|
|
|
|
|
|
config X86_KPTI
|
2022-03-09 12:05:12 +01:00
|
|
|
bool "Kernel page table isolation"
|
2019-11-20 08:28:17 +01:00
|
|
|
default y
|
|
|
|
depends on USERSPACE
|
|
|
|
depends on !X86_NO_MELTDOWN
|
|
|
|
help
|
|
|
|
Implements kernel page table isolation to mitigate Meltdown exploits
|
|
|
|
to read Kernel RAM. Incurs a significant performance cost for
|
|
|
|
user thread interrupts and system calls, and significant footprint
|
|
|
|
increase for additional page tables and trampoline stacks.
|
|
|
|
|
2020-09-15 12:58:51 +02:00
|
|
|
config X86_EFI
|
|
|
|
bool "EFI"
|
|
|
|
default y
|
|
|
|
depends on BUILD_OUTPUT_EFI
|
|
|
|
help
|
|
|
|
Enable EFI support. This means you build your image with zefi
|
|
|
|
support. See arch/x86/zefi/README.txt for more information.
|
|
|
|
|
2022-04-21 00:19:56 +02:00
|
|
|
config X86_EFI_CONSOLE
|
|
|
|
bool
|
|
|
|
depends on X86_EFI && X86_64 && !X86_VERY_EARLY_CONSOLE
|
2022-06-27 07:06:13 +02:00
|
|
|
select EFI_CONSOLE
|
2023-11-24 12:38:02 +01:00
|
|
|
default y if !UART_CONSOLE
|
2022-04-21 00:19:56 +02:00
|
|
|
help
|
|
|
|
This enables the use of the UEFI console device as the
|
|
|
|
Zephyr printk handler. It requires that no interferences
|
|
|
|
with hardware used by the firmware console (e.g. a UART or
|
|
|
|
framebuffer) happens from Zephyr code, and that all memory
|
|
|
|
used by the firmware environment and its page tables be
|
|
|
|
separate and preserved. In general this is safe to assume,
|
|
|
|
but no automatic checking exists at runtime to verify.
|
|
|
|
Likewise be sure to disable any other console/printk
|
|
|
|
drivers!
|
|
|
|
|
2024-03-04 19:39:03 +01:00
|
|
|
config PRIVILEGED_STACK_SIZE
|
|
|
|
# Must be multiple of CONFIG_MMU_PAGE_SIZE
|
|
|
|
default 4096 if X86_MMU
|
|
|
|
|
2019-06-12 23:03:45 +02:00
|
|
|
source "arch/x86/core/Kconfig.ia32"
|
2019-06-25 18:36:17 +02:00
|
|
|
source "arch/x86/core/Kconfig.intel64"
|
2015-03-12 23:15:28 +01:00
|
|
|
|
2015-10-09 12:20:52 +02:00
|
|
|
endmenu
|