michaelh/zephyr
1
0
Fork 0
Code Releases Activity
zephyr/soc/riscv32/openisa_rv32m1
History
Maureen Helm bc9f67f97f arch: soc: riscv32: Separate soc offsets from soc context save 
The zero-riscy core on the rv32m1 soc does not implement hardware loop
extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it
does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes
from GEN_SOC_OFFSET_SYMS().

Split out the soc offset symbols into a separate config so we can enable
them without enabling soc context saving.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-05-06 14:52:17 -05:00
..
CMakeLists.txt soc: riscv32: add RV32M1 SoC as openisa_rv32m1 2019-01-25 11:59:46 -05:00
Kconfig soc: riscv32: add RV32M1 SoC as openisa_rv32m1 2019-01-25 11:59:46 -05:00
Kconfig.defconfig arch: soc: riscv32: Separate soc offsets from soc context save 2019-05-06 14:52:17 -05:00
Kconfig.soc drivers: i2c: rv32m1: add I2C driver for the RV32M1 RI5CY SoC 2019-04-18 16:04:23 -05:00
linker.ld soc: riscv32: openisa_rv32m1: Link .srodata section 2019-03-13 17:02:05 -05:00
soc.c all: Add 'U' suffix when using unsigned variables 2019-03-28 17:15:58 -05:00
soc.h all: Add 'U' suffix when using unsigned variables 2019-03-28 17:15:58 -05:00
soc_context.h arch: soc: riscv32: Separate soc offsets from soc context save 2019-05-06 14:52:17 -05:00
soc_irq.S arch: soc: riscv32: Separate soc offsets from soc context save 2019-05-06 14:52:17 -05:00
soc_offsets.h arch: soc: riscv32: Separate soc offsets from soc context save 2019-05-06 14:52:17 -05:00
soc_ri5cy.h soc: riscv32: add RV32M1 SoC as openisa_rv32m1 2019-01-25 11:59:46 -05:00
soc_zero_riscy.h soc: riscv32: add RV32M1 SoC as openisa_rv32m1 2019-01-25 11:59:46 -05:00
vector.S soc: riscv32: add RV32M1 SoC as openisa_rv32m1 2019-01-25 11:59:46 -05:00
wdog.S soc: riscv32: add RV32M1 SoC as openisa_rv32m1 2019-01-25 11:59:46 -05:00