bc9f67f97f
The zero-riscy core on the rv32m1 soc does not implement hardware loop extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes from GEN_SOC_OFFSET_SYMS(). Split out the soc offset symbols into a separate config so we can enable them without enabling soc context saving. Signed-off-by: Maureen Helm <maureen.helm@nxp.com> |
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| .. | ||
| arc | ||
| arm | ||
| nios2 | ||
| posix | ||
| riscv32 | ||
| x86 | ||
| x86_64/x86_64 | ||
| xtensa | ||
| Kconfig | ||