8ef8e8b497
In order to support Linux rproc loading, some SOCs require the boot-vector and irq-vectors to be placed into a defined memory area for the mcu to boot. This is necessary for NXP's IMX SOCs for instance but can be leveraged by other SOCs that have multiple zephyr,flash choices. Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
194 lines
6.4 KiB
Plaintext
194 lines
6.4 KiB
Plaintext
# ARM architecture configuration options
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "ARM Options"
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depends on ARM
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config ARCH
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default "arm"
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config CPU_CORTEX
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bool
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help
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This option signifies the use of a CPU of the Cortex family.
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config ARM_CUSTOM_INTERRUPT_CONTROLLER
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bool
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help
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This option indicates that the ARM CPU is connected to a custom (i.e.
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non-GIC or NVIC) interrupt controller.
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A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
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allow interfacing to a custom external interrupt controller and this
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option must be selected when such cores are connected to an interrupt
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controller that is not the ARM Generic Interrupt Controller (GIC) or
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the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC).
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When this option is selected, the architecture interrupt control
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functions are mapped to the SoC interrupt control interface, which is
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implemented at the SoC level.
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N.B. Since all Cortex-M cores have a NVIC, if this option is selected it
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is assumed that the custom interrupt control interface implementation
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assumes responsibility for handling the NVIC.
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config ROMSTART_RELOCATION_ROM
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bool
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default n
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help
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Relocates the rom_start region containing the boot-vector data and
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irq vectors to the region specified by configurations:
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ROMSTART_REGION_ADDRESS and ROMSTART_REGION_SIZE
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This is useful for the Linux Remoteproc framework that uses the elf-loader
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such that it is able to load the correct boot-vector (contained in rom_start)
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into the correct memory location independent of the chosen zephyr,flash
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ROM region.
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Most SOCs include an alias for the boot-vector at address 0x00000000
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so a default which might be supported by the corresponding Linux rproc driver.
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If it is not, additionnal options allows to specify the addresses.
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In general this option should be chosen if the zephyr,flash chosen node
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is not placed into the boot-vector memory area.
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While this aims at generating a correct zephyr.elf file, it has the side
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effect of enlarging the bin file. If the zephyr.bin file is used to boot the
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secondary core, this option should be disabled.
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Example:
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on IMX7D, the chosen zephyr,flash can be OCRAM/OCRAM_S/TCM/DDR memories
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for code location. But the boot-vector must be placed into OCRAM_S for the
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CORTEX-M to boot (alias 0, real 0x00180000/32K available).
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if ROMSTART_RELOCATION_ROM
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config ROMSTART_REGION_ADDRESS
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hex
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default 0x00000000
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help
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Start address of the rom_start region.
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This setting can be derived from a DT node reg property or specified directly.
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A default value of 0x00000000 might work in most cases as SOCs have an alias
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to the right memory region of the boot-vector.
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Examples:
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-IMX7D the boot-vector is OCRAM_S (0x00180000, aliased at 0x0).
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-IMX6SX the boot-vector is TCML (0x007F8000, aliased at 0x0).
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-IMX8MQ the boot-vector is TCML (0x007E0000, aliased at 0x0).
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-IMX8MN the boot-vector is ITCM (0x007E0000, aliased at 0x0).
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Example of DT definition:
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$(dt_nodelabel_reg_addr_hex,ocram_s_sys)
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config ROMSTART_REGION_SIZE
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hex
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default 1
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help
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Size of the rom_start region in KB.
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Default is 1KB which is enough to store the boot and irq vectors.
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This setting can be derived from a DT node reg property or specified directly.
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Example for IMX7D that needs the boot-vector into OCRAM_S (0x00180000):
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$(dt_nodelabel_reg_size_hex,ocram_s_sys,0,K)
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endif
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config CODE_DATA_RELOCATION_SRAM
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bool "Relocate code/data sections to SRAM"
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depends on CPU_CORTEX_M
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select CODE_DATA_RELOCATION
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help
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When selected this will relocate .text, data and .bss sections from
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the specified files and places it in SRAM. The files should be specified
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in the CMakeList.txt file with a cmake API zephyr_code_relocate(). This
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config is used to create an MPU entry for the SRAM space used for code
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relocation.
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config ARM_ON_ENTER_CPU_IDLE_HOOK
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bool
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help
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Enables a hook (z_arm_on_enter_cpu_idle()) that is called when
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the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
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If needed, this hook can be used to prevent the CPU from actually
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entering sleep by skipping the WFE/WFI instruction.
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config ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
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bool
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help
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Enables a hook (z_arm_on_enter_cpu_idle_prepare()) that is called when
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the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
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If needed, this hook can prepare data to upcoming call to
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z_arm_on_enter_cpu_idle(). The z_arm_on_enter_cpu_idle_prepare differs
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from z_arm_on_enter_cpu_idle because it is called before interrupts are
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disabled.
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config ARM_ON_EXIT_CPU_IDLE
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bool
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help
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Enables a possibility to inject SoC-specific code just after WFI/WFE
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instructions of the cpu idle implementation.
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Enabling this option requires that the SoC provides a soc_cpu_idle.h
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header file which defines SOC_ON_EXIT_CPU_IDLE macro guarded by
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_ASMLANGUAGE.
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The SOC_ON_EXIT_CPU_IDLE macro is expanded just after
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WFI/WFE instructions before any memory access is performed. The purpose
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of the SOC_ON_EXIT_CPU_IDLE is to perform an action that mitigate issues
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observed on some SoCs caused by a memory access following WFI/WFE
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instructions.
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rsource "core/Kconfig"
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rsource "core/Kconfig.vfp"
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# General options signifying CPU capabilities of ARM SoCs
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config CPU_HAS_ARM_MPU
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bool
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select CPU_HAS_MPU
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help
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This option is enabled when the CPU has a Memory Protection Unit (MPU)
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in ARM flavor.
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config CPU_HAS_NXP_MPU
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bool
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select CPU_HAS_MPU
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help
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This option is enabled when the CPU has a Memory Protection Unit (MPU)
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in NXP flavor.
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config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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bool "Custom fixed SoC MPU region definition"
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help
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If enabled, this option signifies that the SoC will
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define and configure its own fixed MPU regions in the
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SoC definition. These fixed MPU regions are currently
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used to set Flash and SRAM default access policies and
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they are programmed at boot time.
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config CPU_HAS_ARM_SAU
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bool
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select CPU_HAS_TEE
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help
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MCU implements the ARM Security Attribution Unit (SAU).
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config CPU_HAS_NRF_IDAU
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bool
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select CPU_HAS_TEE
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help
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MCU implements the nRF (vendor-specific) Security Attribution Unit.
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(IDAU: "Implementation-Defined Attribution Unit", in accordance with
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ARM terminology).
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config HAS_SWO
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bool
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help
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When enabled, indicates that SoC has an SWO output
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endmenu
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