Add sam4e_xpro in the integration_platform list to build the
atmel,sam_udp compabitle driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
SAM4E doesn't have PLLB, so the USB clock must be derived from PLLA
which is shared with the system clock.
Use PMC_MCKR_CSS_PLLB_CLK to detect PLLB availability at compile time:
- SAM4S (has PLLB): Use dedicated PLLB, 96MHz / 2 = 48MHz
- SAM4E (no PLLB): Use PLLA, ~240MHz / 5 = 48MHz
For SAM4E, PLLA is already configured by the SoC init code for the
system clock, so we just verify it's locked and configure the USB
divider. On shutdown, we don't disable PLLA since it's needed for
the system clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add CONFIG_SOC_ATMEL_SAM_MCK_PRESCALLER to allow configure the
Master Clock (MCK) prescaler. This is needed for SAM4E which
requires a prescaler of 2 to achieve the correct clock frequency.
Changes:
- Add SOC_ATMEL_SAM_MCK_PRESCALLER Kconfig option with default of 2 for
SAM4E and 1 for other SAM series
- Fix SOC_ATMEL_SAM_PLLA_MULA default for SAM4E from 9 to 19 to achieve
120MHz: 12MHz * 20 / 2 = 120MHz
- Use CONFIG_SOC_ATMEL_SAM_MCK_PRESCALLER in SoC init for
SAM4E, SAM4S, SAMX7X
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add a new USB Device Controller (UDC) driver for Atmel SAM4S, SAM4E,
and SAM3S microcontrollers with the UDP (USB Device Port) peripheral.
This driver replaces the deprecated legacy USB stack before removal.
Hardware Specifications:
- USB 2.0 Full-Speed only (12 Mbps)
- 8 hardware endpoints (EP0-EP7)
- 2668 bytes embedded DPRAM/FIFO
- No DMA - all transfers via PIO
- Integrated transceiver with pull-up on DDP
- Dual-bank (ping-pong) support on EP1,2,4,5,6,7
Endpoint Configuration (per datasheet Table 40-1):
- EP0: Control, no dual-bank, 64 bytes
- EP1,2: Bulk/Iso/Int, dual-bank, 64 bytes each bank
- EP3: Bulk/Int, no dual-bank, 64 bytes
- EP4,5: Bulk/Iso/Int, dual-bank, 512 bytes each bank
- EP6,7: Bulk/Iso/Int, dual-bank, 64 bytes each bank
Key Implementation Details:
1. Dual-Bank Pipelining (IN transfers):
- Track filled banks with tx_banks counter (0-2)
- Set TXPKTRDY after each bank fill per datasheet 40.6.2.2
- Pre-fill second bank while first is transmitting
2. OUT Processing:
- Bulk/Int endpoints processed directly in ISR
- EP0 uses thread-based processing for control transfer flexibility
- Bank alternation tracking for dual-bank endpoints
3. Clock Management:
- PLLB configured for 48MHz USB clock (UDPCK)
- Proper suspend/resume with clock gating
- Transceiver disable during disconnect for power saving
4. CSR Register Handling:
- Special "write 1 to preserve" bits handled correctly
- Polling after set/clear for MCK/UDPCK synchronization
- RX_DATA_BK0, RX_DATA_BK1, RXSETUP, STALLSENT, TXCOMP preserved
5. Endpoint Allocation Strategy:
- Odd endpoints (1,3,5,7) for IN, even (2,4,6) for OUT
- EP0 for control transfers
Performance:
- Achieves ~800-900 KB/s throughput
- Near USB Full-Speed theoretical maximum (~1.2 MB/s)
- All testusb tests (0-29) passing
Tested on sam4s_xplained board with Linux testusb utility.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add devicetree nodes for the UDP peripheral on SAM4S and SAM4E SoCs,
along with the corresponding devicetree binding.
The UDP controller is present at:
- SAM4S: 0x40034000, IRQ 34
- SAM4E: 0x40084000, IRQ 35
Both variants share the same compatible "atmel,sam-udp" and feature:
- 8 hardware endpoints (EP0-EP7)
- 1 bidirectional endpoint (EP0 for control)
- 5 IN endpoints, 4 OUT endpoints
- Full-speed USB 2.0 (12 Mbps)
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The pcf857x_port_set_raw() function has a race condition where
the lock is only taken after the I2C write to update the cached
outputs_state. This allows concurrent threads to read stale
outputs_state values and compute tx_buf based on outdated data.
Since PCF8574/PCF8575 devices have a single output register that
is written atomically (all pins at once), a stale read causes one
thread's pin changes to be overwritten by another thread's write.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Change the arguments of `cfb_invert_area`, `cfb_print`, and
`cfb_draw_(point|line|rect|circle)`, which used unsigned integers to
specify coordinates to signed integers.
This is because coordinate are usually specify with real numbers,
so it is difficult to use unless negative numbers are accepted.
We clip drawings outside the drawable area on the implementation side.
Accordingly, we will update the API version to 0.10.0.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add documentation for new NXP drivers introduced in Zephyr 4.4:
- Temperature sensor driver (nxp,tempsense)
- DAC driver (nxp,hpdac)
- DMA driver (nxp,4ch-dma)
- Hwspinlock driver (nxp,sema42)
These entries were added to their respective subsections in the
release notes to inform users about the new hardware support.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The bits cell for KINETIS_SIM_DMA_CLK and KINETIS_SIM_DMAMUX_CLK was
incorrectly set to 0x00000002 (a bitmask), but the driver passes this
value directly as the bit-shift index to CLK_GATE_DEFINE(). The HAL
defines:
kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U)
kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U)
Fix the bit index to 1 in both nxp_k6x.dtsi and nxp_k8x.dtsi.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Update the clock-cells documentation to describe the 32-bit `name` (id)
cell encoding produced by KINETIS_SIM_CLOCK(). The explicit offset and
bits cells are retained with a note that they exist for consumers such as
the ADC16 driver that read them directly rather than via clock_control.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace direct comparison of the DT `name` cell against kCLOCK_* SDK
enum values with KINETIS_SIM_CLOCK_DECODE_NAME(), which extracts the
clock_name field from the encoded id cell produced by KINETIS_SIM_CLOCK().
A local DT_CLOCK_NAME() helper wraps the decode for readability.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace raw clock_ip_name_t cast with a structured decode of the
encoded `id` clock cell introduced by the KINETIS_SIM_CLOCK() macros.
The sub_system pointer carries a 32-bit encoded value. Extract it via
(uint32_t)(uintptr_t)sub_system and use the KINETIS_SIM_CLOCK_DECODE_*()
macros to retrieve gate_offset, gate_bit and clock_name. This avoids
relying on a C bitfield struct overlay (implementation-defined bit
ordering) or undefined pointer casting behaviour.
Also add mcux_sim_validate_gate_offset() which checks that the decoded
gate register offset is word-aligned and within the SIM register region
size declared in DT, returning -EINVAL if not. This prevents a malformed
clock specifier from accidentally enabling or disabling an unintended
peripheral gate.
Remove the LOG_ERR call and the entire logging module infrastructure
(LOG_LEVEL define, log.h include, LOG_MODULE_REGISTER) since no log
calls remain in the file. This also eliminates the GNU statement
expression extension warning triggered by LOG_ERR macro expansion
under -Wpedantic.
The NXP_KINETIS_SIM_NODE macro is moved to the top of the file so it
can be shared by both the validation helper and the clkout_source /
clkout_divider property accessors.
Fix pinctrl_nxp_port.c to pass the encoded `id` cell (name) as the
clock subsystem instead of constructing CLK_GATE_DEFINE() directly
from the explicit offset/bits DT cells. The old approach bypassed
the new encoding and caused PORT clocks to not be enabled, resulting
in UART pins not being muxed and no serial output.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Update frdm_mcxc444.dts and frdm_mcxc242 overlay files to use the new
KINETIS_SIM_CLOCK() macro form, replacing raw 3-cell clock specifiers.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace all raw 3-cell clock specifiers in nxp_mcxc_common.dtsi with
KINETIS_SIM_CLOCK() macro calls. CMP and VREF legacy alias specifiers
are replaced with their real SCGC4 gate addresses (bits 19 and 20);
DMA and DMAMUX are replaced with their SCGC7/SCGC6 gate addresses.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace all raw 3-cell <&sim KINETIS_SIM_FOO 0xOFFSET BIT> specifiers
with the new KINETIS_SIM_CLOCK() macro. The macro encodes gate offset,
gate bit, and clock name into the first (id) cell while keeping the
explicit offset/bits as the 2nd and 3rd cells for ADC16 and other
consumers that read them directly.
ENET and ENET_1588 legacy alias specifiers (which used invalid out-of-range
clock-name values) are replaced with their real SCGC2 gate register
addresses (offset 0x1028, bit 26).
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add KINETIS_SIM_CLOCK() and KINETIS_SIM_CLOCK_MUX() macros that encode
gate offset, gate bit, clock name, and optional mux configuration into
the 32-bit `name` (id) cell of a 3-cell SIM clock specifier. The bit
layout matches the kinetis_sim_clk bitfield struct used by the driver:
gate_offset[31:19] | gate_bit[18:14] | clock_name[13:9] |
mux_val[8:6] | mux_shift[5:1] | has_mux[0]
DECODE helper macros are also provided for use by the driver and soc.c
to extract individual fields from the encoded cell at compile time.
The existing KINETIS_SIM_* clock-name constants are kept unchanged as
they align with clock_name_t enum values used for CLOCK_GetFreq().
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add counter to the supported features list for Ai-Thinker and DoiTing
Bouffalo Lab boards.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Register bflb_timer devices in the counter_basic_api test suite.
Signed-off-by: William Markezana <william.markezana@gmail.com>
# Conflicts:
# tests/drivers/counter/counter_basic_api/src/test_counter.c
# Conflicts:
# tests/drivers/counter/counter_basic_api/src/test_counter.c
counter_handlers.c was missing verifier/marshaling coverage for multiple
counter APIs, especially 64-bit helpers.
This change adds the missing z_vrfy handlers and corresponding mrsh
includes so the syscall layer matches the public counter API surface.
Missing functions now covered in drivers/counter/counter_handlers.c:
z_vrfy_counter_get_frequency_64
z_vrfy_counter_us_to_ticks_64
z_vrfy_counter_ticks_to_us_64
z_vrfy_counter_ns_to_ticks
z_vrfy_counter_ns_to_ticks_64
z_vrfy_counter_ticks_to_ns
z_vrfy_counter_ticks_to_ns_64
z_vrfy_counter_reset
z_vrfy_counter_set_value
z_vrfy_counter_set_value_64
z_vrfy_counter_get_max_top_value_64
z_vrfy_counter_set_top_value_64
z_vrfy_counter_set_channel_alarm_64
z_vrfy_counter_get_top_value_64
z_vrfy_counter_get_guard_period_64
z_vrfy_counter_set_guard_period_64
z_vrfy_counter_get_pending_int was removed from the macro as it
returns a uint32_t and not exactly an int.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add secproxy_mailbox_flush_thread() to clear stale messages from
rx thread when enabling a channel. Read and discard all pending
messages to ensure clean thread state and prevent errors from
previous unclean state.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Replace single shared interrupt with per-channel interrupt support.
Change .irq to .interrupts[] array in config, use LISTIFY macros
for ISR generation and connection, add channel_enable[] array for
per-channel state tracking. Each rx channel now has independent ISR.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Split interrupt configuration from am64x_r5.dtsi into individual
R5F core files (am64x_r5f0_0.dtsi, am64x_r5f0_1.dtsi,
am64x_r5f1_0.dtsi, am64x_r5f1_1.dtsi) as each core uses
different mailbox channels and VIM interrupt line mappings.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Add interrupt-names property to binding to enable per-channel
interrupt lookup via DT_INST_IRQ_BY_NAME(). Each channel's
interrupt is identified by name: "rx_0", "rx_1", "rx_2", etc.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Remove duplicate error validation in ISR and send path that is
already performed by secproxy_verify_thread(). Remove error mask
checks, message queue fullness checks, and unused
SECPROXY_MAILBOX_NUM_MSGS macro.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Forward actual error codes from secproxy_verify_thread() instead
of masking all errors as -EBUSY. Now returns -EINVAL,
-EBUSY, or -ENODATA from secproxy_mailbox_send() to aid debugging.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Remove busy wait from secproxy_verify_thread() to return immediately
with error status. If mailbox is full, waiting for message processing
is unnecessary and blocks execution until timeout, reporting a timeout
error message reducing debuggability.
The mailbox driver should only return the appropriate error code.
Any required retry logic can be implemented in the caller layer.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
The winc1500_socket function returns a socket index that was only
being checked for negative error values. Coverity identified that
the index was not being verified against the upper bound of the
socket_data array, potentially leading to an out-of-bounds write.
Added an explicit check to ensure the socket index is within the
valid range [0, CONFIG_WIFI_WINC1500_OFFLOAD_MAX_SOCKETS].
Fixes#84708
Signed-off-by: David J. Leach, Jr. <tasmar@gmail.com>
When SHA is activated in the DT, configure it's register region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
