When CONFIG_BT_DEVICE_NAME_DYNAMIC is enabled, write the device name
(restored from flash or the compile-time default) to the BR/EDR
controller during commit_settings().
Replace the bt_set_name() call with a direct strncpy into bt_dev.name
to avoid an unnecessary flash write, then explicitly push the name to
the BR/EDR controller via bt_br_write_local_name().
Signed-off-by: Kai Cheng <chengkai@xiaomi.com>
Extract the HCI Write Local Name command into a reusable
bt_br_write_local_name() helper and use it in bt_br_init().
When CONFIG_BT_DEVICE_NAME_DYNAMIC and CONFIG_BT_SETTINGS are
both enabled, skip writing the compile-time default here since
the settings commit callback will push the correct name (either
restored from flash or the default) to the controller.
Signed-off-by: Kai Cheng <chengkai@xiaomi.com>
Add sample application demonstrating TMCM-3216 stepper control.
This tests all the functions of both stepper driver and controller.
Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
Added all device nodes for TPM to be used as PWM, as there are already
some device nodes for TPM which are used as counter, so using different
name for TPM which are used as PWM.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
- Enable common/erase_blocks/interface_test/negative_tests
cases on frdm-imxrt1186.
- Test these cases passed on frdm-imxrt1186 cm33/cm7 cores
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Add support for i.MX RT118x in flash driver negative tests by
defining TEST_FLASH_START and TEST_FLASH_SIZE macros.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- configure flexspi2 pinmux
- enable flexspi2 status as ok
- correct jedec id value
- test flash_shell case passed on cm33/cm7 cores
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Configure FLEXSPI2 root clock using SYS_PLL3_PFD2 with divider 2
when FLEXSPI2 is enabled and not used for XIP flash
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Enable the counter_basic_api test for Realtek Bee series SoCs.
Add configurations for the following boards:
- rtl87x2g_evb_a_rtl8762gku
- rtl8752h_evb_rtl8752hjl
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add counter timer driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver is based on the hardware timer and supports:
- Relative alarm configuration
- Top value configuration
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add the microchip,rgmii-delay binding for KSZ9131 PHYs and use it
on the SAMA7G54-EK board DTS.
GMAC0 on SAMA7G54-EK is connected to a KSZ9131 PHY over RGMII and
requires internal delay configuration equivalent to rgmii-id for
reliable gigabit operation.
Add KSZ9131 RGMII DLL delay configuration using Clause-22 indirect
MMD access.
The KSZ9131 PHY uses MMD device 2, registers 76 and 77, to control
RXC and TXC DLL delay bypass. Configure these registers according
to the requested RGMII delay mode:
- none
- id
- rxid
- txid
Delay setting would be skipped for variants that do not support RGMII
like KSZ9131MNX
Signed-off-by: Balaji Vasudevan <balaji.vasudevan@microchip.com>
BOARD_GrantTRDCFullPermissions() flow:
- Request TRDC ownership via ELE for AON/MEGA/WAKEUP
- Apply SDK-aligned DAC (including TRDC3 MDAC assignments)
- Grant full access control settings for TRDC1/TRDC2
Refactor the implementation out of soc.c into a dedicated trdc_setup.c
file to keep soc.c focused on early init sequencing, and add it to the
SoC CMakeLists.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
1. Enable XIP by default since the reset vector is located in flash,
and disable dcache to avoid losing cached data after reset.
2. Also define WDT_MAX_WINDOW for andestech_atcwdt200.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
1. Setting aliases name(watchdog0) for adp_xc7k's watchdog
2. Default runs in XIP mode because the default reset_vector is
located in flash.
3. Also disable dcache to avoid losing cached data after reset.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Add support for the CONFIG_WDT_DISABLE_AT_BOOT Kconfig option.
If the watchdog timer is enabled by default on the target board,
enabling this option will explicitly disable the watchdog during
the driver initialization phase.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
- Gate off M7 clock before clearing M7_CFG[WAIT] (CPUWAIT) and gate
it back on after the deassert. (This is the process requirement
in RT118X RM)
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Rx packet notified from low layer with an
error status are skipped and the rx failure
is notified to upper layer through
the IEEE802154_EVENT_RX_FAILED event
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add HSE Trimming operation through the board_late_init_hook()
process.
HSE Tuning value is getting from OTP.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add HSE Trimming operation through the board_late_init_hook()
process.
HSE Tuning value is getting from OTP.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
SiWx91x includes a Network Co-Processor (NWP). The firmware of the NWP is
tightly coupled to the version of the WiseConnect SDK. Until now, the user
had to retrieve the associated firmware manually (with a risk of taking an
outdated version).
Until now, the user had to retrieve the NWP firmware manually. It was
painful and error prone. We now provide the NWP firmware as a blob and
describe how to flash it.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
siwx917_rb4338a and siwx917_rb4342a are very similar. Let's factorize the
device trees of these boards.
More factorization (mainly about documentation) could be applied in the
future.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Commit 8e2326e43 ("boards: silabs: siwx91x: add ADC configuration for
siwx917 boards") changed the pin used for ADC on brd4342 but not on
brd4338. Yet, brd4338 has the same schematic. So, align the pinout of the
two boards.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Refactor the PWM capture interrupt handler to properly support all
three capture channels (A, B, and X).
Clear capture FIFOs by reading CVAL registers during enable_capture
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add feature check to ensure these functions are only called when the
hardware supports input filter capture registers.
Update device tree binding documentation to clarify that the
input-filter-count and input-filter-period properties only take
effect when the capture input filter register is available.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
- Deletes virtual "nxp,cmc-reset-cause" compatible,
as it is covered by existing "nxp,cmc".
- Fixes the issue discovered during discussion in
https://github.com/zephyrproject-rtos/zephyr/issues/104464
#issuecomment-3957779329
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The default value 0x200 wasn't compatible with IVT alignment which was
set to 0x400 due to large number of ISR.
Signed-off-by: Petr Buchta <petr.buchta@nxp.com>
updated the devicetere for mspm0x515 and lx22x to mention the rtc-x
property which identifies it as the RTC_A or RTC_B variant.
Signed-off-by: Jackson Farley <j-farley@ti.com>
