Increase the reset pulse from 10ms to 100ms to ensure reliable
boot across all Espressif SoCs. Shorter pulses may cause the UART
to miss early bootloader output, leading to false-positive test
failures.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For the ina226 shunt voltage is implemented and supported,
unfortunatly it was forgotten to select
INA2XX_HAS_CHANNEL_SHUNT_VOLTAGE.
Since 70423db9d1c69d32597ba1f7b2fe66569014a4b0 it will
no longer build. This fixes it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Update the MIPI DBI ESP32 driver to match the renamed/split LCD HAL
APIs from the latest hal_espressif sync:
- soc/gdma_channel.h moved to hal/gdma_channel.h
- lcd_ll_set_data_width() split into lcd_ll_set_dma_read_stride()
and lcd_ll_set_data_wire_width()
- lcd_ll_enable_rgb_yuv_convert() renamed to
lcd_ll_enable_color_convert()
Also update west.yml hal_espressif revision.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a check of the URI scheme length before comparing it
to any instance's supported URI schemes. If the incoming
URI scheme is longer than what we support, then there's
no point in checking if we support it, as we cannot.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Add IRQ numbers for RTC1 and RTC2 alarm on the IT8xxx2 interrupt
controller for RTC driver support.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Added pic32cx_sg41_cult.overlay file for tc.
Added board support in main.c
Added an extra scenario to testcase.yaml
Signed-off-by: Farsin Nasar V A <farsin.nasarva@microchip.com>
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
- Added overlay file for running the sample application
- Updated main.c to use tc instance for running it
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
The BT_GATT_INCLUDE_SERVICE is always included in
BT_MCS_SERVICE_DEFINITION even when CONFIG_BT_OTS=n,
this fixes it such that it is only included when OTS is enabled.
Fixes zephyrproject-rtos#105345
Signed-off-by: Vedant Malkar <vedantitsme@gmail.com>
Some UART drivers (for example nrfx) might return -EBUSY, if we
try sequence of close->change baud->open without any delay.
Instead, close the UART pipe and wait for BUS_CLOSED event before
reconfiguring the baud rate.
Then wait for the timeout to pass, before continuing with dial script.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
This test uses alias 'watchdog0' instead of label name.
Update YAML filter to use dt_alias_exists and moving this check to the
beginning of the filter expression for better understanding of scenario
requirements.
This fix is from PR #102950.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Co-authored-by: Yves Wang <zhengjia.wang@nxp.com>
This sample uses alias 'watchdog0' instead of label name.
Update YAML filter to use dt_alias_exists and moving this check to the
beginning of the filter expression for better understanding of scenario
requirements.
This fix is from PR #102950.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Co-authored-by: Yves Wang <zhengjia.wang@nxp.com>
Adds default partitioning bl_storage UICR areas which can be used
for bootloader storage purposes
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add empty branch MCUX_SIRC_CLK in clock on to avoid incorrect return
value for drivers which use this clock.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
This commit addresses two issues during ISR restoration:
1. Support IRQ_DIRECT_CONNECT: Compare the current RAM vector table
against Zephyr's initial flash vector table (`_vector_start`)
instead of hardcoding `_isr_wrapper`. This correctly identifies
ROM-patched ISRs without falsely overriding Zephyr direct ISRs.
2. Prevent race conditions: Add `irq_lock()` and reorder
`NVIC_EnableIRQ` to safely handle driver interrupts that might
already be active during late initialization.
Note: There is a known limitation with this approach. If a user
registers a direct ISR on an IRQ that the ROM also registers, the
ROM's ISR will take precedence. However, this overlap is practically
rare as users do not typically override ROM-owned interrupts.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add initialization of critical components for the RTL8752H
series.
Key initializations include:
- Realtek OS abstraction layer.
- Clock active mode settings.
- Power Management (PM).
- PHY modules.
- Bluetooth controller ROM initialization.
Note: A mechanism is introduced to synchronize the RAM Vector Table between
Realtek's ROM code (which writes raw ISRs) and Zephyr's interrupt
management subsystem (sw_isr_table).
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
The OSIF API signature for `os_msg_queue_create` differs between the
RTL8752H series and other supported SoCs (e.g., RTL87x2G). Specifically,
the RTL8752H implementation does not accept a queue name string as an
argument.
This commit adds a conditional check using `CONFIG_SOC_SERIES_RTL8752H`
to invoke the correct API variant. This ensures the test suite compiles
and runs correctly on both RTL8752H and RTL87x2G platforms.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
This commit refactors the Realtek OSIF (Operating System Interface)
implementation to support multiple SoCs within the Bee family and
introduces support for the RTL8752H series.
Previously, the OSIF implementation was tightly coupled with the
RTL87x2G series. To facilitate the addition of new SoCs, the
architecture has been restructured into a common layer and
SoC-specific layers:
1. Common Layer: The generic Zephyr wrapper implementations have
been moved to `osif/common/osif_zephyr_impl.c`. This code is
now shared across different Realtek SoCs.
2. SoC-specific Layer: The function pointer assignments (ROM patch
initialization) are now separated into SoC-specific files
(e.g., `osif_zephyr_patch.c`).
Based on this new architecture, the RTL8752H series support is added
by providing its specific patch initialization while reusing the
common Zephyr wrappers.
The file structure changes are as follows:
- generic wrappers: Moved to `osif/common/osif_zephyr_impl.c`
- RTL87x2G patch: Moved to `osif/rtl87x2g/osif_zephyr_patch.c`
- RTL8752H patch: Added in `osif/rtl8752h/osif_zephyr_patch.c`
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
The &trng node was enabled in the shared ek_ra8d2.dtsi, but it is
only referenced by the CM85 variant. This caused build failures on
the CM33 variant with '__device_dts_ord_DT_CHOSEN_zephyr_entropy_ORD'
undeclared errors across many test suites.
Move trng enablement to ek_ra8d2_r7ka8d2kflcac_cm85.dts so
it is only enabled for the CM85 variant that actually uses it
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
On mcxw70, the flash cache is managed by the underlying driver from
hal_nxp. The method used in the soc_flash_mcux driver is not suitable
for this platform, and should be disabled.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
- Add NBU pinmux to configure HDI mode with external radio
- Define nbu_handler to the MU interrupt handler
- Enable TSTMR0 clock at init
- Enable connectivity framework, MCMGR, rpmsg-lite
- Enable MU driver when selecting NXP_RF_IMU
- Disable LPUART1 to avoid pin conflicts with radio interface
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
When using an external radio, we need to configure pins for HDI mode.
Since it's specific to NBU, we can add this control in the nxp_nbu
driver.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Move the "ranges" property to the main smu2 definition.
This makes sure the smu2 properties are centralized at the same
location.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Define a shared memory section in STCM, this shared memory is used
to transmit data to the NBU core.
This shared STCM section must be used through non-secure address range
because the NBU core can only access non-secure memory regions, and
the main core must reference non-secure addresses in the data shared
with the NBU core.
Since the MCXW70 doesn't have an SMU2, reworked the sections.ld file
to use a macro-based approach to determine the node label.
This allows to differentiate devices that have SMU2 from those that
don't, while reusing the same sections.ld file.
Use "stcm_shared" as node label for MCXW70.
Use node status in sections.ld since all regions are not available
on all SoCs.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add testcase and corresponding overlay for native_sim to test
the FTL (Flash Translation Layer) disk driver.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add disk names for zephyr,ftl-dhara disks to FF_VOLUME_STRS, so that
they are available for mounting.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Zephyr has currently no flash translation layer implemented. This commit
adds the basic possibility to use Dhara as FTL in Zephyr. It is
implemented as disk driver that can be placed between a filesystem and a
flash driver.
Signed-off-by: Pascal Linder <pascal.linder@zuehlke.com>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
NAND flash translation layers require the flash extended operations API
for bad block management. Add it here without implementation to test an
FTL on the flash simulator.
Signed-off-by: Pascal Linder <pascal.linder@zuehlke.com>
Add extended operations to the flash API to support marking blocks
as bad and checking if a block is bad. This is necessary for
NAND flash devices, which can have bad blocks that need to be managed.
Signed-off-by: Pascal Linder <pascal.linder@zuehlke.com>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
When the controller supports BR/EDR and CONFIG_BT_CLASSIC is
enabled, call bt_br_init() to perform the full BR/EDR Classic
initialization (SSP mode, inquiry mode, local name, Class of
Device, etc.).
For non-Classic builds that still need BR/EDR buffer sizes,
gate the hci_read_buffer_size() fallback with
IS_ENABLED(CONFIG_BT_CONN) to make the build-time condition
explicit at the call site.
Signed-off-by: Kai Cheng <chengkai@xiaomi.com>
When CONFIG_BT_CLASSIC is enabled and the controller is ready,
push the updated device name to the BR/EDR controller via
bt_br_write_local_name() inside bt_set_name(). This ensures
runtime name changes are properly synchronized to the BR/EDR
transport.
Signed-off-by: Kai Cheng <chengkai@xiaomi.com>
