Adds runtime device power management support to MAX32 Wake-up Timer
driver. The suspend routine is intentionally left unimplemented to
allow the Wake-up Timer to continue counting while the device is in
sleep mode.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add Zephyr itself, with its CPE and PURL, to the modules-deps.spdx file, to
have one accurate SBoM for vulnerability scanning. Also add DEPENDENCY_OF
relationships to be able to build up a dependency-graph with the
modules-deps.spdx SBoM
Signed-off-by: Nils Schlegelmilch <n.schlegelmilch@vega.com>
Co-authored-by: Benjamin Cabé <benjamin@zephyrproject.org>
MSIS and MSIK requires either LSE at 32.768kHz or HSE at 16MHz or 32MHz
to enable their PLL mode for auto-calibration.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct assertion on MSIS/MSIK PLL mode configuration regarding
dependency on LSE clock rate and MSIS/MSIK source clock.
While at it, replace the runtime assertion with a build time assertion
and move all the MSIS/MSIK configuration assertion outside
set_up_fixed_clock_sources() local function.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix stm32_clock_control.h to not define twice STM32_MSI_ENABLED
which may hurt some toochains even if defined to the same value.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix stm32_clock_control.h that could test STM32_MSI_PLL_MODE value
with the macro possibly not being defined.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Change STM32_LSE_ENABLED, STM32_MSIS_ENABLED and STM32_MSIK_ENABLED
macros to not be defined when the related clock is not enable in Zephyr
scope. This is their expected state where used in the implementation
(e.g., relying on #ifdef) but at a few places regarding STM32_LSE_ENABLED
that are also fixed by this change. While at it, replace two runtime
assertions with build time assertions.
This change makes these macros more consistent with the other
main clock enable state macros (STM32_LSI_ENABLED, STM32_HSI_ENABLED,
STM32_HSE_ENABLED, etc...).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This reverts commit c691c22cdc.
Initially test required alias `watchdog0`.
At some point, testcase.yaml was extended with filter checking
if `dt_nodelabel_enabled("watchdog0")` is True.
This resulted in skipping the test on many platforms because
there was an alias, not a label.
Commit c691c22cdc adds
node label `watchdog0` to overlays for Nordic targets.
https://github.com/zephyrproject-rtos/zephyr/pull/105209
Fixed the filter by changing `dt_nodelabel_enabled("watchdog0")`
to `dt_alias_exists("watchdog0")`.
Node labels are no longer needed. Revert commit that adds them.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
This test has been seen timing out in CI, on what are most likely just
slower or more loaded runners. Let's just increase the timeout.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Select the correct radio sequencer image on xG24 and xG26 at
compile time instead of deferring the selection to runtime.
This saves 16 kB of the binary size.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add xG28-EK2705A Explorer Kit for the xG28 dual-band SoC.
The board has 2 buttons and LEDs in addition to Qwiic and
mikroBUS connectors and an on-board debugger.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Don't rely solely on disconnect events to determine writability, since
the socket can drop at any time. A send() to a closed socket fails and
the resulting error reaches the shell thread, where a failing __ASSERT
causes a crash.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
Guard the websocket shell backend's internal state with a mutex.
The disconnect callback executes on a different thread than the shell
and can interleave with sends, leading to writes on an invalid fd or
a disconnected socket.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
The MPC is currently set up to allow R,W,X,Priv access to all RAM
and MRAM for all cores. This is not sufficient if CONFIG_USERSPACE
is enabled, in which case the application core will be accessing
memory unprivileged, using the MPU to manage memory access.
Update MPC configuration to allow R,W,X,Unpriv access to all RAM and
MRAM for all cores. The R,W,X MPC configuration has to be applied
regardless of CONFIG_USERSPACE, so no need to conditionally include
the MPU configuration based in CONFIG_USERSPACE.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Travis Lam <travis.lam@nordicsemi.no>
Fix two bugs in the timer counter driver that prevent tests
from passing.
-EBUSY should be returned from set_top_value() if there are
active alarms, not if the counter has been started.
The ISR should only process interrupts that are currently enabled,
not all pending flags.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Enable UART_NS16550_TI_K3 driver by default for AM6X A53 cores.
This ensures the TI K3 specific UART variant is used on A53 cores,
matching the configuration already enabled for M4 and R5 cores.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
add a function to set the IP offload plugin,
similar to the already existing net_if_socket_offload_set().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
- Change `config SMF` to `menuconfig SMF` since it serves as a parent
for child config options under `if SMF`.
- Update help text descriptions to follow Zephyr wording conventions,
replacing descriptions with clearer explanations.
Signed-off-by: Vladislav Kulikov <vlad_kulikov_c@pm.me>
Enable `PSA_WANT_ALG_HMAC` in ciphersuites that enable
`PSA_WANT_ALG_TLS12_PRF`.
The former is a dependency of the latter which Mbed TLS enables
automatically in its configuration files but not all PSA Crypto
implementations do that.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
Pass the function argument `dev` to the async callback instead of
`data->uart_dev`. The pointers are identical, but `dev` is already
available in this context, so it's clearer to use it directly.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add Ethernet support including:
- Board initialization code with PHY reset handling
- Device tree definitions for ethernet
- PHY link state tracking fixes in ethernet driver
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
The edma0 interrupts list had 16 entries (IRQs 0-15) but
was missing DMA_ERROR_IRQn (IRQ 16). The eDMA driver treats
the last entry as the error IRQ, so IRQ 15 (DMA15_DMA31
transfer-complete) was misused as the error handler. This
broke DMA channels 15 and 31 entirely.
Add <16 0> as the 17th entry.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add the CRC peripheral to DTSI of STM32 SoCs.
(Note: CRC is not added to SoC series STM32F1, STM32F2, STM32F4, STM32L1
and some STM32F0 SoCs because their CRC peripheral is not supported by
the driver due to HW limitations - this matches the binding's description)
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Create option CONFIG_CRC_STM32_DMA_THRESHOLD used to select between CPU and
DMA copy based on buffer size. Depending on the application and hardware,
it can be faster to perform a CPU copy for small buffer sizes than request
a DMA transfer: this options allows limiting DMA usage only to buffers of a
large enough size.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a new driver for the STM32 CRC. The driver is instance-aware and
supports data transfers using DMA.
Co-authored-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a binding for the STM32 CRC calculation unit. Note that this binding
only covers the programmable variant of the CRC peripheral: the older CRCv1
found in series such as STM32F1/F2/F4/L1 and some STM32F0 products is not
supported due to HW limitations.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
