Extend the ESP32 LEDC PWM driver to support ESP32-C5. Clear the
gamma RAM fade function on SoCs that have it to prevent stale
fade parameters from affecting duty cycle output.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the ESP32 GDMA driver to support ESP32-C5. Add the C5 SoC to
the AHB GDMA configuration and define the per-channel interrupt
source mappings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add ESP32-C5 support to the RTC counter driver. The C5 uses a
different LP timer interrupt status register field
(soc_wakeup_int_st) compared to other SoCs (alarm), requiring a
SoC-specific macro for the interrupt status check.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend UART and USB serial drivers to support ESP32-C5. Add UHCI0
compatibility macro since the ESP32-C5 HAL exports the UHCI
peripheral as UHCI instead of UHCI0.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add CLIC interrupt controller support for ESP32-C5. Set the SHV
(selective hardware vectoring) bit for each allocated interrupt
so the CLIC dispatches through the mtvt vector table.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the ESP32 GPIO driver to support ESP32-C5 by adding the
SoC series to the register struct compatibility defines.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disable the interrupt before reconfiguring its type to prevent
spurious triggers and edge detector asymmetry. Without this, the
first gpio_pin_interrupt_configure(GPIO_INT_EDGE_BOTH) can leave
the edge detector in an inconsistent state causing a persistent
timing offset between rising and falling edge detection.
Also skip the enable call when the requested mode is disable,
avoiding a redundant enable immediately after setting the type to
GPIO_INTR_DISABLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add devicetree source files, clock definitions, interrupt mapping,
GPIO signal map, and pin control bindings for ESP32-C5.
Also add 8 MB flash partition layout with 0x2000 offset and extend
the espressif,riscv CPU binding to accept 48 MHz XTAL frequency.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add SoC-level support for the ESP32-C5, Espressif's first dual-band
Wi-Fi 6 SoC with a RISC-V core clocked up to 240 MHz and 384 KB SRAM.
The ESP32-C5 uses a CLIC interrupt controller (not PLIC like ESP32-C6).
CLIC requires special handling for mret to restore mintstatus.mil from
mcause.mpil: bit 31 (interrupt flag) must be set in mcause before mret,
otherwise mil is not restored and interrupts at the same level are
permanently blocked. This is handled via RISCV_SOC_CONTEXT_SAVE with
mcause and mintthresh save/restore in soc_irq.S, following the same
pattern used by GD32VF103 (Nuclei ECLIC) and Nordic VPR.
The systimer on ESP32-C5 always runs at 16 MHz regardless of the XTAL
frequency (40 or 48 MHz), which requires a SoC-specific override for
SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds the support of timers for STM32C5. This includes all timer instances
for the series, and the support of the counter, PWM and QDEC drivers.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add all the bindings that were added in Zephyr 4.4 to date to the
corresponding sections of the release notes.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add all the samples that were added in Zephyr 4.4 to date to the
corresponding sections of the release notes.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add all the shields that were added in Zephyr 4.4 to date to the
corresponding sections of the release notes.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add all the boards that were added in Zephyr 4.4 to date to the
corresponding sections of the release notes.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Boards must live in a folder named after the vendor prefix, therefore
Qualcomm boards belong to boards/qcom.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
In earlier changes, `ai_m62_12f` and `ai_wb2_12f` have been renamed to
`ai_m62_12f_kit` and `ai_wb2_12f_kit` in a breaking way, whereas we
would usually rely on boards/deprecated.cmake to give folks a deprecation
warning.
This change updates the deprecated list accordingly and moves the
rename notice from release notes to migration guide.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This allows user threads to test if they have permission to access
an object before attempting to perform an operation on it and fail
gracefully if not.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
This reduces the typical number of instructions executed on interrupt by
one and saves an additional 3-4 instructions on syscall, by two
related optimizations.
* The top bit of `mcause` indicates an interrupt, and the RISC-V ISA
specification suggests checking the sign of `mcause` to separate
interrupts from exceptions. Doing so saves one instruction in
generating an intermediate value to compare against and comparing to
zero instead. In the exception branch, this doesn't modify the
temporary value and saves one instruction in not needing to reload
with the value of `mcause`.
* Loading a register with `CONFIG_RISCV_MCAUSE_EXCEPTION_MASK` and
masking `mcause` with that requires two instructions at minimum, and
three if the mask is too large to fit into a single instruction.
Since the first optimization leaves the temporary value of `mcause`
unmodified and it is known that the interrupt bit is clear after the
branch to `is_interrupt`, reloading and masking the value of `mcause`
can be skipped entirely.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
This option was formerly enabled by sy1xx, but all supported socs now
appear to use the standard behavior so this support can be removed.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Add timer subnodes under the MAX32657 Wake‑up Timer device nodes to
enable system timer configuration in devicetree.
Also set default SYS_CLOCK_TICKS_PER_SECOND to 8192 if Wake-up Timer is
selected as system timer.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Introduce a system timer driver that uses the MAX32 Wake-up Timer as the
system tick source. This enables the MAX32 SoC family to use the WUT for
kernel timing operations.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Enable the on-chip BLE HCI controller on the DT-XB1 board by
setting the bt-hci node status to "okay" and adding the
zephyr,bt-hci chosen node.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add an HCI driver for the BL702 on-chip BLE controller. The controller
is a precompiled binary blob communicating via vendor on-chip HCI
functions (bt_onchiphci_send/bt_onchiphci_interface_init).
The driver:
- Translates between Zephyr HCI net_buf and the vendor's internal
packet structures for both TX (commands, ACL data) and RX (events,
ACL data)
- Uses a dedicated RX thread with FIFO+semaphore to dequeue messages
from the controller callback (which may run in ISR context)
- Reads the BLE MAC address from eFuse during initialization
- Supports multiple controller binary variants via Kconfig choice
(peripheral-only, multi-role, observer, etc.)
- Provides proper open/close lifecycle with RX queue draining
Also adds the DT binding (bflb,bl70x-bt-hci) and a bt-hci node in
the BL70X SoC dtsi (disabled by default).
Signed-off-by: William Markezana <william.markezana@gmail.com>
# Conflicts:
# drivers/bluetooth/hci/CMakeLists.txt
Add platform shims, FreeRTOS compatibility layer, and linker scripts
to support the BL702 on-chip BLE controller binary blob under Zephyr.
The BLE blob expects a FreeRTOS environment and vendor HAL functions.
This commit provides:
- FreeRTOS API shim (xTaskCreate, xQueueGenericSend, pvPortMalloc,
etc.) mapping to Zephyr kernel primitives (k_thread, k_msgq,
k_malloc)
- Platform shims for bl_irq_*, bl_timer_*, BL702_Delay_*, GLB_*,
and UART stub functions the blob references
- RF calibration callbacks required by libbl702_rf.a
- Linker scripts placing BLE/FreeRTOS ROM writable data regions and
__global_pointer$ for GP-relative addressing from ROM code
- ROM function address table (PROVIDE symbols) as fallback for
un-shimmed FreeRTOS functions
- HAL module CMakeLists selecting controller library variant and
linking BLE/RF blobs
- Exchange memory configuration (8KB) when BLE is enabled
- RISCV_NO_MTVAL_ON_FP_TRAP selection for FPU trap handling
Signed-off-by: William Markezana <william.markezana@gmail.com>
Update hal_bouffalolab module revision to include BLE controller
binary blobs, RF library, and header files for the BL702 SoC family.
Also fixes a typo in the bt_onchiphci_handle_rx_acl declaration.
Signed-off-by: William Markezana <william.markezana@gmail.com>
# Conflicts:
# west.yml
Add driver for the QST QMI8658A 6-axis inertial measurement unit
with accelerometer and gyroscope. Supports I2C bus, configurable
full-scale range and ODR via devicetree, temperature readout, and
optional data-ready interrupt trigger on INT2.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add QST Corporation to the list of known vendor prefixes. This is
needed for the QMI8658A IMU sensor driver.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Enable SRAM retention and device runtime power management on MAX32
SoCs when backup mode is enabled so that OS can properly restore
state and resume execution after exiting backup mode.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
If runtime power management is enabled for idle mode timer, it must be
explicitly resumed after waking up from suspend-to-RAM modes. Call
pm_device_runtime_put() before suspending to decrement the usage counter
so that pm_device_runtime_resume() can successfully resume the device
after wake up.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Increase the default UART logging backend buffer size to reduce the
frequency of pm_device_runtime_get()/put() calls triggered for each
batch of output.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
