Update FlexCAN clock configuration across NXP MCXN family boards to use
PLL0 as clock source with a divider of 3 instead of FRO_HF with divider
of 1.
The new configuration provides FlexCAN peripherals by using the PLL0
output (150MHz) divided by 3 to achieve 50MHz, replace previous 48MHz
FRO_HF.
Signed-off-by: William Tang <william.tang@nxp.com>
Add CAN FD support for MCXN SOC family, including mcxn23x, mcxn94x
and mcxn54x.
Tested with tests/drivers/can.
Fixes#91138
Signed-off-by: William Tang <william.tang@nxp.com>
Add support for the DFRobot Beetle ESP32-C3 board. This is a small IoT
development board based on the Espressif ESP32-C3 RISC-V SoC.
Board features:
- ESP32-C3 (32-bit RISC-V at 160MHz)
- 400KB SRAM, 4MB Flash
- 2.4GHz WiFi and BLE
- 13x IO ports
- Integrated lithium battery charging management
The board has been tested with the following Zephyr samples:
- samples/basic/blinky
- samples/hello_world
- samples/net/wifi/shell
Signed-off-by: Mikołaj Rosowski <m.rosowski1@wp.pl>
Update the NXP FlexCAN migration guide entry to take the latest Kconfig to
devicetree change into account.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Rename the Aesc Silicon platform label used on GitHub to match the rest of
the platform labels.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Document breaking changes in prescale-glitch-filter configuration
and the new prescale-glitch-filter-bypass property. Provide migration
example for out-of-tree device trees.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Fix incorrect LPTMR prescaler/glitch filter mapping that led to wrong
frequency calculation and wrong hardware configuration.
- Calculate effective counter frequency correctly:
* Time Counter mode: divide by 2^(value + 1)
* Pulse Counter mode: divide by 2^value
- Map prescale-glitch-filter directly to the HAL enum (no offset math)
- Add prescale-glitch-filter-bypass DT boolean (default false)
- Restrict prescale-glitch-filter to 0..15 and update bindings/DTS users
- Add build-time validation for Pulse mode (value 0 requires bypass)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Adjust the pin function bitfield to 4 bits to fit all RZ/V SoCs
(RZ/V2L, V2H, V2N). PFC bitfield of RZ/VH, V2N have 4 bits, so
the current 3-bit width does not fit them.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
If api->trylock(dev, id) fails (typically because a cross-core
HW lock is held by another core and returns -EBUSY, or returns
-EINVAL, etc.), the function will immediately return the error
code, but the local ctx->lock is not released, and interrupts
also remain in the locked state from the trylock. This may cause
IRQ lock state leakage. If there's no opportunity in the call path
to reach k_spin_unlock(), the system may exhibit unpredictable
"freeze-like" behavior.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The macro names sys_port_trace_k_fifo_put_slist_enter/exit in
tracing.h were incorrectly named and did not match the corresponding
definitions in backend implementations.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Remove the CONFIG_CAN_MCUX_FLEXCAN_MAX_MB configuration option from
the documentation notes, as the message buffer count information has
been moved to the devicetree and no longer needs to be described in
Kconfig.
Update the constraint for CONFIG_CAN_MCUX_FLEXCAN_MAX_FILTERS to
reflect that it must be less than the maximum number of message
buffers supported by the FlexCAN instance, as shown in the table
below the note. This keeps same behavior as driver.
Signed-off-by: William Tang <william.tang@nxp.com>
This change refactors the FlexCAN driver to use per-instance message
buffer configuration instead of global Kconfig options. The driver now
calculates message buffer allocation at compile time based on device
tree properties for each FlexCAN instance.
Key changes:
- Remove global CAN_MAX_MB Kconfig option and associated range constraint
- Add number_of_mb, rx_mb, and tx_mb fields to mcux_flexcan_config
structure
- Move callback arrays and atomic allocation bitmaps from static global
arrays to per-instance static arrays generated by macros
- Update data structure to use pointers to per-instance arrays instead
of fixed-size embedded arrays
- Add compile-time validation to ensure sufficient message buffers are
available for required RX filters and RX filters greater than 0
This approach allows different FlexCAN instances to have different
message buffer configurations based on their hardware capabilities
and device tree settings, improving memory efficiency and flexibility.
The change maintains backward compatibility while enabling better
resource utilization across different SoC variants.
Fixes#92798
Signed-off-by: William Tang <william.tang@nxp.com>
Add the `number-of-mb` and `number-of-mb-fd` device tree property to
all the NXP FlexCAN controller nodes across various SoC families to
specify the maximum number of 8-byte and 64-byte payload message
buffers supported by each FlexCAN instance.
This change updates device tree source files for multiple NXP SoC
families including Kinetis K6x, RT10xx, RT11xx, RT118x, MCX, S32K,
S32Z, and i.MX8MP/i.MX93 series. The property values are set based
on hardware specifications for each specific FlexCAN instance.
This property addition ensures proper resource allocation and
prevents buffer overflow issues in FlexCAN driver implementations.
Signed-off-by: William Tang <william.tang@nxp.com>
Removing the esp32s3_devkitm as deprecated and redundant.
The esp32s3_devkitc has essentially the same functionality.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Introduce the I2C_CODE_IN_RAM option to place selected critical
functions into the RAM code section.
This allows latency-sensitive I2C paths to execute from RAM when
required, while keeping the default behavior unchanged.
NOTE1: Enable I2C_CODE_IN_RAM on it81202bx: RAM size +2272B.
NOTE2: With kernel in RAM, enabling I2C_CODE_IN_RAM saves ~558ms
over 1,000 transfers (W/R/W2R), tested on it81202bx.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix WWDT warning interrupt by configuring ITRC to not intercept WWDT
timeout events.
ROM may configure ITRC OUT3_SEL0/OUT4_SEL0 to route WWDT0-2 to ITRC,
causing ITRC to reset the system faster than WWDT, preventing the
warning interrupt from functioning. Reconfigure these registers to
0xAAAAAA0A to allow RSTCTL to properly handle WWDT reset events.
Also enable WWDT warning interrupt in the board configuration to ensure
proper watchdog interrupt handling during tests.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The WWDT callback is only invoked from the warning interrupt path.
If CONFIG_WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG is 0, the warning
interrupt is effectively disabled, so a configured callback would
never fire.
Return -ENOTSUP and log an error when a callback is provided
without enabling the warning interrupt, to avoid a silent no-op.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Correct the WWDT window value calculation and add proper
range validation.
The window value was incorrectly set to the minimum timeout value.
Per hardware specification, it should be calculated as:
windowValue = timeoutValue - min_window_ticks
Also add:
- MAX_TIMEOUT boundary checks
- Validation before value assignment
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Move pinctrl_apply_state() from configure to init to ensure pinctrl
is applied once at boot rather than on every transaction.
When cs-gpios is defined, spi_context_cs_configure_all() runs after
pinctrl and reconfigures the CS pin as GPIO, properly overriding
any CS routing set by pinctrl.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Implement read_c45 and write_c45 functions to support clause 45
register access. This enhancement allows to access C45 registers
even when the MDIO controller does not natively support clause 45.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Use clause 45 MDIO access by default and only fallback to the phy
internal clause 45 bridge if the MDIO controller does not support
clause 45 transactions.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
DAT3-based card detection may fail for the first attempt on RT1060evkc
+ NXP_IW610x_v1 card, caused by transient signal states during
initialization. Set IMX_USDHC_DAT3_DETECT_RETRY as 10 can fix this issue.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
DAT3-based card detection can return a false negative on the first read
due to transient signal states after enabling detection. Add a bounded
retry loop (limited by IMX_USDHC_DAT3_DETECT_RETRY) with a short delay
between attempts to improve robustness.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
The /soc node is a simple-bus node and not an interrupt provider. Leaving
the #interrupt-cells property produces misleading Device Tree build
warnings:
Warning (interrupt_provider): /soc: '#interrupt-cells' found, but node is
not an interrupt provider <stdout>: Warning (interrupt_map): Failed
prerequisite 'interrupt_provider'.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Add the SOC_IT8XXX2_RAM_CODE_NOINLINE Kconfig option to prevent
functions marked with __soc_ram_code from being inlined when LTO
is enabled.
This ensures RAM code functions remain in the RAM section instead of
being merged into callers by the compiler.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adds doxygen documentation for the extended API of the Texas Instruments
TLC5971 LED strip controller driver.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Similar to how it's done for other driver classes, create a new doxygen
group to put all device-specific LED strip API extensions under.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The current driver implementation only support pooling and
synchronous operations. By adding DMA support the driver will
be able to operate in asynchronous mode which helps to improve
CPU usage and save power.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
