To simplify usage add dependecy to MAX32_ON_ENTER_CPU_IDLE_HOOK
If CONFIG_PM not defined set to to y as current,
If CONFIG_PM defined not set it
If user set CONFIG_PM not need to disable
MAX32_ON_ENTER_CPU_IDLE_HOOK anymore
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
MAX32657 is Cortex-M33 based Analog Devices MCU.
It supports ARM TrustZone security model.
There will be two boards of this MCU Secure and Non-Secure
This commit defines Secure version of peripherals.
Basic feature of MAX32657 device:
- Core is Cortex-M33
- 50MHz IPO clock
- There are 54 interrupt vectors
- 1MB flash & 256 SRAM
- MAX32657 has:
- 1 x UART
- 1 x I2C/I3C
- 1 x SPI
- 6 x TIMER
- 1 x RTC
- 1 x WDT
- 1 x TRNG
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
The symbol SRAM_VECTOR_TABLE is not used in the adi/max32 soc. Removed
it in order to clean up the Kconfig file and avoid confusion with the
upcoming new definition of SRAM_VECTOR_TABLE symbol. (PR #87468)
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Adds support for the primary m4 core to configure the boot address and
start the clock for the secondary risc-v core. Unlike the msdk which
defers this function to applications and requires users to copy/paste
code from an msdk example application into their own application, in
zephyr it is implemented in the common soc init routine of the primary
core. It can be enabled/disabled and configured with Kconfig symbols and
a devicetree chosen node, allowing applications to override board-level
defaults if desired using overlays instead of modifying zephyr code.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Refactors the max32 soc family configuration to allow socs with cores
other than arm cortex-m4. This will make it possible to add support for
the secondary risc-v core that exists on some max32 variants.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
The SystemCoreClock variable must be placed in the '.shared' section for
the MAX78000 and MAX78002 because the ARM core is responsible for changing
the System Clock and updating the SystemCoreClock variable, and the
RISC-V core knows what the System Clock frequency is through the
shared variable.
Signed-off-by: Yasin Ustuner <Yasin.Ustuner@analog.com>
Extracts the max32 flashprog linker section to a dedicated linker script
that is conditionally included only when the flash driver is enabled.
This prepares max32 soc family to set SOC_LINKER_SCRIPT directly to the
common arm cortex-m linker script.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Sets CONFIG_HAS_SEGGER_RTT on the max32 soc family to allow using RTT
backends in the logging, shell, and tracing subsystems.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
MAX32xxx
MAX32655
MAX32655EVKIT
MAX32655FTHR
MAX32666
MAX32666FTHR
MAX32666FTHR2
MAX32690
MAX32690EVKIT
MAX78xxx
MAX78000
MAX78002
...
When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.
If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.
To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n
MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.
Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
