Commit graph

59480 commits

Author SHA1 Message Date
Daniel Leung
8308f3f4d5 lib: os: introduce memory blocks allocator
This introduces yet another memory blocks allocator where:

() All memory blocks have a single fixed size.

() Multiple blocks can be allocated or freed at the same time.

() A group of blocks allocated together may not be contiguous.
   This is useful for operations such as scatter-gather DMA
   transfers.

() Bookkeeping of allocated blocks is done outside of
   the associated buffer (unlike memory slab). This allows
   the buffer to reside in memory regions where these can be
   powered down to conserve energy.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-11 16:10:53 -05:00
Daniel Leung
5604b98f21 lib: os: group heap related kconfigs under a menu
This groups the heap related kconfigs under a menu
so they are under a group (!).

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-11 16:10:53 -05:00
Daniel Leung
0f7c31e0a4 math: introduce macro for integer log2
This introduces macro for calculating integer log2.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-11 16:10:53 -05:00
Dawid Niedzwiecki
d361b8e30d adc: add io-channel-cells to use io-channels
Add fragment:
io-channel-cells:
    - input
to binding of the "ite,it8xxx2-adc" and "zephyr,adc-emul" compatible.
It is necessary to use io-channels property.

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2022-01-11 14:47:16 -06:00
Henrik Brix Andersen
13e6d264bb samples: modules: canopennode: add stm32f3_disco support
Add support for the ST STM32F3 Discovery development board.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-11 14:40:49 -06:00
Henrik Brix Andersen
d727547f79 modules: canopennode: increase stack sizes
Increase the default CANopenNode stack sizes a bit. The current stack
sizes are too small for e.g. ST STM32F3, likely other platforms as well.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-11 14:40:49 -06:00
Marc Herbert
8a603da6cd twister: add -Werror to CMAKE_AFLAGS
This reports the warning fixed in commit 61fe69dded ("sys:
device_mmio.h replace <toolchain/common.h> with <toolchain.h>")

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-01-11 12:32:27 -05:00
Marc Herbert
19e4e12c03 twister: remove spurious quoting of EXTRA_xFLAGS=-Werror
Testing shows cmake is invoked directly, not through a shell.

Fixes commit 5092541e2b ("sanitycheck: disable erroring on warnings").
Note EXTRA_AFLAGS was quoted only on the left side!

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-01-11 12:32:27 -05:00
Gerard Marull-Paretas
864888f2ce soc: arm: nuvoton_npcx: add missing include
The reg_def.h was not self-contained: it uses DT API but doesn't
include <devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 10:03:54 -05:00
Piotr Golyzniak
483101fe36 twister: raise error for non-existing platform call
Changes will raise error and break program in following three situations:

1. Platform name pass in --platform option does not exist.
2. During using --all option, platform from platform_allow list does not
exist.
3. During using --integration option, platform from
integration_platforms list does not exist.

Signed-off-by: Piotr Golyzniak <piotr.golyzniak@nordicsemi.no>
2022-01-11 09:53:40 -05:00
Erwan Gouriou
7c25fd3c2e boards: doc: Clarify a generic statement
This sentence ("Other hardware features are not supported by the
Zephyr kernel."), which could be found in a high number of boards
documentation, is misleading on two levels:
- peripheral support is not a kernel business
- in most of cases, features are actually supported but not enabled.

Fix this.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-01-11 11:54:22 +01:00
Henrik Brix Andersen
e919db3222 drivers: can: add user_data to state change callback
Add optional user data argument to can_set_state_change_callback() to
comply with Zephyr API design guidelines.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-11 11:54:04 +01:00
Andy Ross
3457118540 kernel/smp: Fix races in SMP initialization
This has bitrotten a bit.  Early implementations had a synchronous
arch_start_cpu(), but then we started allowing that to be an async
operation.  But that means that CPU start now becomes surprisingly
reentrant to the arch layer (cpu 0 can get a call to start cpu 2 while
cpu 1's initialization code is still running).  That's just error
prone; we never documented the requirements cleanly (the window is
very small, but not so small to a slow simulator!).

Add an extra flag so we don't issue the next start until the last is
out of the arch layer and running in smp_init_top().

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-11 11:53:53 +01:00
Andy Ross
97ada8bc04 arch/xtensa: Promote adsp RPO/cache utilities to an arch API
This is trick (mapping RAM twice so you can use alternate Region
Protection Option addresses to control cacheability) is something any
Xtensa hardware designer might productively choose to do.  And as it
works really well, we should encourage that by making this a generic
architecture feature for Zephyr.

Now everything works by setting two kconfig values at the soc level
defining the cached and uncached regions.  As long as these are
correct, you can then use the new arch_xtensa_un/cached_ptr() APIs to
convert between them and a ARCH_XTENSA_SET_RPO_TLB() macro that
provides much smaller initialization code (in C!) than the HAL
assembly macros.  The conversion routines have been generalized to
support conversion between any two regions.

Note that full KERNEL_COHERENCE still requires support from the
platform linker script, that can't be made generic given the way
Zephyr does linkage.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-11 11:53:53 +01:00
Andy Ross
6aa3d0c72f soc/intel_adsp: Split out mp_cavs.c from soc_mp.c
Continue the previous work, moving the cAVS hardware dependencies into
a separate file, leaving soc_mp.c with only OS-generic details to
track.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-11 11:53:53 +01:00
Andy Ross
9e524d8305 soc/intel_adsp: Refactor mp code to separate hardware from OS details
Clean up soc_mp.c a bit.  Put all cAVS register use in functions
dedicated to hardware details (e.g. "soc_start_core()"), leave the
Zephyr OS tracking (e.g. the CPU start record, the active cores array,
etc...) in generic code.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-11 11:53:53 +01:00
Marcin Niestroj
31425c58d1 soc: esp32: use SoC name as IDF target instead of board name
So far board name was used as IDF target. This worked, as the only board
in tree that is based on 'esp32' SoC is actually 'esp32'.

Use CONFIG_SOC instead of CONFIG_BOARD, so that new boards based on
'esp32' SoC can be successfully introduced both downstream or upstream.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-01-11 11:53:09 +01:00
Alexander Mihajlovic
673806aef1 drivers: spi: stm32: Skip pinctrl setup for subghzspi
Subghzspi instances cannot have any pinctrl configs,
they are blacklisted by the dts binding. This caused an
initialization failure of the spi_ll_stm32 driver for
subghzspi instance because no "default" pinctrl was found.

This commit solves the problem by skipping the pinctrl setup
for subghzpi devices. The use_subghzpi_nss property is used
to identify a subghzspi device, as this is a required boolean
property only available in the subghzspi binding this is a
perfect indicator for such instances.

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2022-01-11 11:52:59 +01:00
Andreas Chmielewski
fbae13122f net: lwm2m: enable monitoring of fw update state/result
The intention behind this patch is to know the current state/result
of a firmware update process in the application code. It makes it
possible to use pre/post_write_callbacks to get the proper value
of state (5/0/3) and result (5/0/5) resource.

Signed-off-by: Andreas Chmielewski <andreas.chmielewski@grandcentrix.net>
2022-01-11 11:52:50 +01:00
Piotr Pryga
bbf19b24be Bluetooth: Controller: llcp: Missing llcp ctx release when disconnect
If there were local LLCP pending and connection lost happened there
were no release of allocated control procedure context.
It caused to exhaustion of available procedures.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2022-01-11 11:52:42 +01:00
Piotr Pryga
3d9784a79e Bluetooth: Controller: change def val BT_CTLR_LLCP_PROC_CTX_BUF_NUM
Default value for CONFIG_BT_CTLR_LLCP_PROC_CTX_BUF_NUM was set to
CONFIG_BT_CTLR_LLCP_CONN, so the value was 1. That caused a problem
if a device had started a local control procedure and remote procedure
request was received. Ther there were no free context for remote
procedure.

The commit changes the range of allowed value to start from 2.
Also the default value is set to two if CONFIG_BT_CTLR_LLCP_CONN
is 1. In other case default value is set to number of CONFIG_BT_-
LLCP_CONN.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2022-01-11 11:52:42 +01:00
Tim Lin
263fd9d1d1 ITE: cleanup: it8xxx2: drivers/intc rename the function
The function should be renamed ite_intc_irq_polarity_set.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:52:35 +01:00
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
a84a16f8ff arch: arm: aarch32: cortex_m: nvic: make header self-contained
The header contains macros that make use of the Devicetree API, however,
<devicetree.h> is not included. This was "mitigated" by most <soc.h>
including <devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
31ad52336b soc: riscv: telink_b91: fix required headers
The linker script is using the DT API, which was previously included via
<soc.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
130b06a0fd soc: riscv: riscv-privilege: andes_v5: make smu.h self contained
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
a08e87e078 soc: arm: silabs_exx32: make soc_pinmap.h self contained
The soc_pinmap.h uses the DT API, so these headers needs to include
<devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
7a5ee28755 soc: arm: atmel_sam0: common: soc_port: add missing include
The source file uses boolean types internally, however, <stdbool.h> was
not included. It was likely included indirectly before via
<devicetree.h> -> <sys/util.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
095a21e2cf soc: arm: nuvoton_npcx: make soc_*.h headers self-contained
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Tim Lin
96203820db boards: it8xxx2_evb: add aliases of i2c0
Add the aliases, we are able to build test of
tests/drivers/i2c/i2c_api for the it8xxx2_evb board.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:51:04 +01:00
Tim Lin
d676b51485 ITE: drivers/i2c: add the API of get configuration
This commit adds the API of get_config that will make test of
tests/drivers/i2c/i2c_api pass on it8xxx2_evb board.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:51:04 +01:00
Marius Scholtz
14e15df00f drivers: arm: stm32: adc: Added Shared IRQ
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.

Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.

Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
2022-01-11 11:50:43 +01:00
Gerard Marull-Paretas
412c051fbf codeowners: add GD32 RISC-V boards
Add myself as a code owner for GD32 RISC-V boards.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
5523528144 maintainers: add GD32 RISC-V boards to GD32 Platforms
Add RISC-V GD32 official boards (e.g. gd32vf103v_eval) to the file list
in the GD32 Platforms section.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
97cc216957 tests: drivers: gpio: gpio_basic_api: add support for gd32vf103v_eval
Add DT overlay to run gpio_basic_api test on GD32VF103V-EVAL board. In
order to make testing easy a couple of accessible pins have been
selected: PD0 and PD1 pins exposed via JP13 and JP4 respectively.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
a4790bcfab boards: riscv: gd32vf103v_eval: initial support
Add initial support for the GD32VF103V-EVAL board. The board is based on
the GD32VF103 RISC-V MCU.

This board can run on Zephyr now largerly thanks to the initial work
done by @soburi.

Note that this board requires using the riscv-openocd fork, however,
programming is slow when using OpenOCD even though it works (including
debugging). J-Link option has also been enabled as it seems to be more
realiable and works _out of the box_. Some details are given in the
board documentation file.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
1e81e7cded drivers: pwm: gd32: enable gd32vf103
Add dependency on SOC_SERIES_GD32VF103. The driver is compatible as is
with this series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
c8a630ab77 dts: riscv: gigadevice: gd32vf103: add timers and pwm
Add entries for timers and PWM devices.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
cdcd11aac0 drivers: gpio: gd32: enable gd32vf103
The device implemented by this driver is also available on GD32 RISC-V
MCUs.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
ddf440fe60 dts: riscv: gigadevice: gd32vf103: include GPIO bindings
Include the GPIO dt-bindings header (required for gpio cells).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
c4269ba947 drivers: interrupt_controller: gd32_exti: enable gd32vf103
The device implemented by this driver is also available on GD32 RISC-V
MCUs.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
806f5de18d dts: riscv: gigadevice: gd32vf103: add exti
Add EXTI node, required by the EXTI and GPIO drivers.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
07eee1bc79 drivers: interrupt_controller: gd32_exti: isr may be unused
The gd32_exti_isr function may be unused if the GPIO driver is not
enabled but EXTI is (no IRQ will connect to it). This may be improved in
the future by requiring explicit enablement of the exti DT node.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Emil Gydesen
43b827c562 zephyr: Add UTF8 kconfig to conditionally compile utf8.c
Add the kconfig option so that the utf8.c file can be
conditionally compile, and only for the applications
that need it.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2022-01-11 11:50:15 +01:00
Emil Gydesen
baf48fbe2e zephyr: Add UTF-8 truncating strlcpy variant
Add a function to copy a UTF-8 encoded string that
ensure correct truncation of the string if the source
is larger than the destination, as well as ensuring that
the resulting destination string is NULL-terminated.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2022-01-11 11:50:15 +01:00
Emil Gydesen
5cb72d2193 zephyr: Add function to properly truncate UTF-8 strings
Add a function that can properly truncate UTF-8 strings
without leaving unterminated started characters,
as UTF-8 characters can be 1-4 bytes long.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2022-01-11 11:50:15 +01:00
Shao Ming
7e318b5e93 soc/intel_adsp: Fix the PFN width in cavs-fw.py loader
Change the PFN field width from 54 to 55 to follow the Linux Doc.
(https://www.kernel.org/doc/html/latest/admin-guide/mm/pagemap.html)
Otherwise issue may arise if physical address beyond 2^66 is mapped.

Refactor the v15 and v25 scripts to extract the common part.
This is to suppress the pylint duplicate code check.

Signed-off-by: Shao Ming <ming.shao@intel.com>
2022-01-11 11:49:53 +01:00
Francois Ramu
0434c1fcb8 tests: drivers: uart async on stm32h743 nucleo board
connect USART2 D53 / TX (pd5) to D52 / RX (pd6)
on the ARDuino connector CN9 of the nucleo board

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-11 11:49:23 +01:00
Tim Lin
45b6aa4c3b ITE: drivers/i2c: add the compatibility of GPIO F2/F3 for i2c3
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.

TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:49:16 +01:00
Jaremy J. Creechley
3ac2ca2aa5 net: socket: extend posix compatability SO_<opts>
Adding these definitions help ease of porting POSIX applications.

They currently do nothing in the core network stack and will
return an error if used. However, they help port some POSIX
without changing these. In particular, this enables using the
Nim programming language's standard library with Zephyr.

- The values copy Linux amd64, similar to the other SO_OPTIONS
- Add SO_SNDBUF to fix simplelink wifi
- Use compat options in simplelink wifi

Signed-off-by: Jaremy J. Creechley <jaremy.creechley@panthalassa.com>
2022-01-11 11:48:16 +01:00