Commit graph

6912 commits

Author SHA1 Message Date
IBEN EL HADJ MESSAOUD Marwa
1e5b2eb235 dts: arm: st: add stm32u0 support
Provide support for the familly STM32U0 and ST32U083

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
2024-08-26 11:28:04 -04:00
Elias Speinle
c4dba39548 drivers: fpga: add driver for renesas slg471X5
add driver for renesas slg471X5

Signed-off-by: Elias Speinle <e.speinle@vogl-electronic.com>
2024-08-26 17:06:14 +02:00
Fabrice DJIATSA
9e4c554487 dts: arm: st: remove clock node from parent node soc
Since the clock node is not a child node of the soc node,
but from the root node.
This removes the warning log at compilation.


Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2024-08-26 11:05:00 -04:00
Lucien Zhao
8077a74621 dts: arm: nxp: add ITCM/DTCM region into linker
add ITCM/DTCM region into linker file

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-08-24 07:16:11 -04:00
Karol Lasończyk
85c292ac59 soc: nordic: Move DCDC configuration to DT for nRF54L15
Moving configuration for nRF54L15 device from kconfig to dts.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
2024-08-23 15:49:52 +01:00
Emil Juhl
f53a401758 drivers: led: lp5569: add enable-gpios
The lp5569 features a double functioning pin for enable and pwm control.
The chip, however, uses the first rising edge to initialize and get ready
for i2c communication, and then the pin alters function to pwm mode.

Add support for providing enable-gpios to the lp5569 in the dts, which
will make sure to assert the pin and wait for the chip to initialize
before attempting further configuration of the chip.

Signed-off-by: Emil Juhl <emdj@bang-olufsen.dk>
2024-08-23 15:49:43 +01:00
Emil Juhl
47f9040bfa drivers: led: lp5569: add charge pump configuration
The lp5569 controller contains an internal charge pump which can be useful
for driving LEDs with a forward voltage greater than the lp5569 supply.
Taking advantage of the charge pump can alleviate the need for an external
boost converter.

Add a dts property, charge-pump-mode, to the ti,lp5569 binding with which
the cp_mode bits of the MISC register will be configured.

Following the datasheet, the possible configurations are:
    0x00 -> disabled (default)
    0x01 -> 1x mode
    0x10 -> 1.5x mode
    0x11 -> auto mode

Signed-off-by: Emil Juhl <emdj@bang-olufsen.dk>
2024-08-23 15:49:43 +01:00
Raffael Rostagno
dfbcb9dd60 dts: irq: esp32: Added priority and flags to device tree
Added IRQ priority and flags configuration to device tree.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-22 14:25:25 -04:00
Raffael Rostagno
f783dec97c bindings: intc: esp32: Added symbols in DT
Added symbols for IRQ priority and flags configuration
in the device tree.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-22 14:25:25 -04:00
Duy Phuong Hoang. Nguyen
b9f31c0e40 drivers: entropy: Initial support for trng driver of RA8
Initial commit for entropy support on RA8
- drivers: entropy: implementation for TRNG driver of RA8x1
- dts: arm: add device node for trng of RA8x1
- boards: arm: enable support zephyr_entropy for ek_ra8m1 and
update board documentation

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-22 14:24:57 -04:00
Emanuele Di Santo
d4b1e1e302 dts: Add initial support for nRF9280 SiP
Add definition of the nRF9280 SiP with its Application,
Radio, and Peripheral Processor (PPR) cores and a basic set
of peripherals: GRTC, GPIOs, GPIOTE, and UARTs and few others.

Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
2024-08-22 14:24:38 -04:00
Lucien Zhao
b919292570 dts: arm: nxp: add all the lpi2c device on device tree
add 6 lpi2c instances on device tree

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-08-22 14:21:27 -04:00
Daniel DeGrasse
17f71e19f0 drivers: sdhc: imx_usdhc: assume card is present if no detection method
The imx USDHC driver previously queried the peripheral's internal card
detect signal to check card presence if no card detect method was
configured. However, some boards do not route the card detect signal and
do not work correctly with the DAT3 detection method supported by this
peripheral. As a fallback, assume the card is present in the slot but
log a warning to the user.

Fixes #42227

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-08-22 14:19:37 -04:00
Emilio Benavente
67b7c993e1 boards: nxp: frdm_mcxn947: Updated Init Clock for LPTMR
Updated the clocks that get initialized for the MCXN947
when using the LPTMR. The LPTMR allows the user to select
and Input clock, however said input clock must be
initialized before the user can select it.
Update description for clk-source in binding file.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2024-08-22 09:16:28 +02:00
Yangbo Lu
e5b6fcd084 dts: arm: nxp: add device tree for i.MX93 Cortex-M33
Added basic device tree file for i.MX93 Cortex-M33.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2024-08-22 09:15:16 +02:00
Felipe Neves
3d39644a2c boards: witte_technology: linum: add initial support
To the Linum board from Witte Technology based on STM32H753xx.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
2024-08-21 18:26:07 +01:00
Tu Nguyen Van
ee6620e15f dts: arm: nxp: add Flexcan support for S32Z27x
Add FlexCan nodes to S32Z27x devices

Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
2024-08-21 11:03:44 +02:00
Tu Nguyen Van
ac056bbab9 dts: arm: nxp: rename can node to canxl node
To prepare for supporting flexcan, can node should be
renamed to canxl to support both flexcan and canxl

Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
2024-08-21 11:03:44 +02:00
TOKITA Hiroshi
0877b3a354 soc: renesas: ra: Add RA2A1 SoC support
Add Support for Renesas RA2A1 SoC.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2024-08-21 08:58:17 +02:00
Dat Nguyen Duy
b7b17fa0eb dts: nxp_rt1010: mark edma channel has separate interrupt entry
In SoC imxrt1010, edma channel has separate interrupt entry,
not like the rest of in-tree imxrt SoC series

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2024-08-20 19:43:05 -04:00
Ricardo Rivera-Matos
6825fc3a9d drivers: haptics: drv2605: Introduces overdrive clamp prop
Adds "vib-overdrive-mv" device tree property to configure the overdrive
clamp at initialization.

Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
2024-08-20 14:52:32 -04:00
Ricardo Rivera-Matos
38b827d18d drivers: haptics: drv2605: Introduces rated voltage prop
Adds support for boot time configuration of the rated voltage at
initialization via "vib-rated-mv" devicetree property.

Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
2024-08-20 14:52:32 -04:00
Ricardo Rivera-Matos
857b9df26e drivers: haptics: drv2605: Pick up property defaults from DT
Adds the default value for the existing properties to the device tree
and fall back on those values at initialization if necessary.

Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
2024-08-20 14:52:32 -04:00
Ricardo Rivera-Matos
7d58579a17 dts: bindings: drv2605: Requires actuator-mode prop
Requires the actuator-mode property to be set as there is no safe
default value.

Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
2024-08-20 14:52:32 -04:00
Ricardo Rivera-Matos
9dc17f76c2 dts: haptics: drv2605: Documents GPIOs
Documents the enable GPI and the input/trigger GPI in the dt bindings.

Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
2024-08-20 14:52:32 -04:00
Fabrice DJIATSA
07cdebaf8e dts: arm: st: add reset control for display peripheral
add reset control registers information (on RCC_BUS_RSTR LTDCRST bit)
for display peripheral reset.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2024-08-20 14:50:57 -04:00
Zhengwei Wang
4a7adb3d9d drivers: spi: pm: Add power management support for Ambiq Apollo3 SoCs SPI
Add power management support for Apollo3/Apollo3P SPI, and
automatically enables device runtime power management

Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
2024-08-20 10:32:52 +02:00
Zhengwei Wang
2cbf3b9365 drivers: i2c: pm: Add power management support for Ambiq Apollo3 SoCs I2C
Add power management support for Apollo3/Apollo3P I2C, and
automatically enables device runtime power management

Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
2024-08-20 10:32:52 +02:00
Zhengwei Wang
03a1fe6cd7 drivers: serial: pm: Add power management support for Apollo3 SoCs UART
Add power management support for Apollo3/Apollo3P UART, and
automatically enables device runtime power management

Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
2024-08-20 10:32:52 +02:00
Zhengwei Wang
1eb831efc3 soc: ambiq: Add power management support for Apollo3 SoCs
This commit adds support for the power management for
Apollo3/Apollo3P SoCs

Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
2024-08-20 10:32:52 +02:00
Joseph Liu
3fb70c677a soc: arm: add nuvoton npcm400 support
Add initial support for nuvoton npcm400, which is a chip
family of Satellite Management Controller(SMC).

Add ecst python scripts to append the header used by ROM Code

Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
2024-08-20 10:32:43 +02:00
Thao Luong
4cebe5354f drivers: adc: initialize to add ADC driver
Add minimal ADC driver code for EK-RA8M1 board

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
2024-08-20 10:31:43 +02:00
Anke Xiao
17ee197635 dts: arm: nxp: nxp_ke1xz.dtsi: add lptmr support
Add lptmr support for ke17z, add related configuration for lptmr
driver.
Add supported CPU power states for idle, stop, partial stop 1, and
partial stop 2.

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-08-19 15:18:33 -04:00
Anke Xiao
1b0a7420d0 dts: arm: nxp: nxp_ke1xz.dts: add wdog support
Add wdog32 support and select 128K LPO clock.

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-08-19 15:18:18 -04:00
Laurentiu Mihalcea
6b689d0207 firmware: scmi: add support for pinctrl protocol
This includes helper function for pin configuration
and a DT binding for the pinctrl DT node.

There's two important notes to be made regarding this
protocol:

* pinctrl drivers have no subsytem API to implement as opposed
to clock control drivers. Because of this (and the fact that
`pinctrl_configure_pins()` doesn't require a `struct device`
handle) the pinctrl driver consists only of a helper function,
which implements the `PINCTRL_CONFIGURE_PINS` command.
Additionally, the `scmi_protocol` structure is defined inside
the pinctrl helpers source file to avoid redundant code
(otherwise, each SCMI-based pinctrl driver would have to define
it its source file).

* each vendor may have their own set of pin propeties and DT
representations for them. Because of this, there can't be a
generic, SCMI-based pinctrl driver. As such, each vendor who
wants to use the SCMI support for pinctrl operations will have
to implement their pinctrl driver (which, to put it simply,
revolves around implemeting `pinctrl_configure_pins()`) and
make use of the pin configuration function introduced in this
commit. Moreover, this means that each vendor will have control
over the way their pin properties are encoded in the
`scmi_pinctrl_settings` structure.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-08-19 10:05:16 -04:00
Laurentiu Mihalcea
350e36a47a firmware: scmi: add support for clock management protocol
This includes:
	1) Source containing helper functions, each
	implementing a command from the clock management
	protocol.

	2) A clock controller driver making use of said
	helper functions and implementing the clock
	subsystem API.

	3) A DT binding for clock protocol node.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-08-19 10:05:16 -04:00
Laurentiu Mihalcea
413c77cf4e firmware: introduce SCMI core support
Introduce core support for ARM's SCMI (System Control and
Management Interface). This includes:

* shared memory (SHMEM) driver. This consists of a suite
of functions used to interact with the shared memory area.

* shared memory and doorbell-based transport layer driver.
Data is passed between platform and agent via shared
memory. Signaling is done using polling (PRE_KERNEL) and
doorbells (POST_KERNEL). This makes use of Zephyr MBOX API
(for signaling purposes) and the SHMEM driver (for polling
and data transfer).

* core driver - acts as glue between transport and protocol
layers. Provides synchronized access to transport layer
channels and channel assignment/initialization.

* infrastructure for creating SCMI protocols

This is based on ARM's SCMI Platform Design Document: DEN0056E.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-08-19 10:05:16 -04:00
Balsundar Ponnusamy
ff9c2f47d3 dts: arm64: intel: add dts node for dma controller for agilex5
add dts support for dma to accomodate dma driver bringup on agilex5

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
2024-08-19 10:02:53 -04:00
Balsundar Ponnusamy
3ab212c1db drivers: dma: add dma driver for designware axi DMA controller
Adding dma driver source for designware axi dma controller

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
2024-08-19 10:02:53 -04:00
Fin Maaß
f775ab4975 drivers: watchdog: litex: add litex watchdog
this adds a driver for the litex watchdog.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-19 10:02:01 -04:00
Mike Banducci
5a8e60b12e soc: stm32: Add support for the stm32h755
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.

Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
2024-08-19 10:01:39 -04:00
Krystof Sadlik
913d6a3e55 dts: bindings: Added bindings for the fxls8974 accelerometer
Added bindings to enable fxls8974 accelerometer

Signed-off-by: Krystof Sadlik <krystof.sadlik@nxp.com>
2024-08-19 10:00:34 -04:00
Chun-Chieh Li
9cf4e1aae5 drivers: usb: udc: change numaker m46x usbd clock source to hirc48m
Change NuMaker M463/M467 series USBD clock source to HIRC48M.
This makes core-clock and its clock source PLL not required
to be multiple of 48MHz.

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
2024-08-19 10:00:07 -04:00
Chun-Chieh Li
3b1d2bb286 soc: nuvoton: numaker: m46x: fix hirc48m typo
Fix typo on HIRC48M. This clock source is required by:
- USB 1.1 OTG PHY
- USBD
- USBH
- OTG

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
2024-08-19 10:00:07 -04:00
Quy Tran
370bd31d2a dts: bindings: clock: Change clock control binding for Renesas RA
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
5f4b9bb0d9 soc: renesas: Add initial support for RA6M4 SoC
- Initial support for RA6M4 SoC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
5f53861508 soc: renesas: Add initial support for RA6M2 SoC
- Initial support for RA6M2 SoC

Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
1e20f0cc22 boards: renesas: Initial support Renesas EK-RA6M1 board
- Initial commit to support EK-RA6M1 board

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
5f454da371 soc: renesas: Add initial support for RA6E2 SOC
Initial support for Renesas RA6E2 SOC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
ed0bdfbee6 soc: renesas: Add initial support for RA6E1 SoC
Initial commit to support RA6E1 SoC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: default avatarQuy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00