Commit graph

6912 commits

Author SHA1 Message Date
Jiafei Pan
f8f359d2c8 board: imx8mm_evk: enable ENET ethernet on Cortex-A Core
Enabled ENET ethernet port on Cortex-A Core for imx8mm EVK board.
Updated suported featues in board document.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-08-12 12:43:54 +02:00
Jiafei Pan
f690b823f9 dts: binding: ethernet-phy: add 1G fixed-link support
Added 1G link support for fixed-link.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-08-12 12:43:54 +02:00
Jiafei Pan
f498644106 drivers: eth: phy: add AR8031 PHY driver
Add PHY driver support for Qualcomm AR8031, it can use fixed link
or use auto negotiation.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-08-12 12:43:54 +02:00
Furkan Akkiz
cfcfea4a26 dts: arm: adi: Add watchdog inside devicetree
Add watchdog peripheral definiton inside device tree file
Add watchdog binding file

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Co-authored-by: Mert Vatansever <Mert.Vatansever@analog.com>
2024-08-11 19:18:56 -05:00
Raffael Rostagno
3dc2e83c7a usb: esp32c6: Add support for USB serial port
Device tree configuration for USB serial node and clock control
fix for proper device initialization.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-11 19:16:35 -05:00
Richard Wheatley
16a2f862ea dts: arm: ambiq: add ambiq rtc to dtsi file
Add Ambiq RTC to DTSI

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2024-08-09 17:58:35 +01:00
Richard Wheatley
8f2413fbe2 dts: bindings: rtc: add ambiq rtc
Add Ambiq rtc binding

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2024-08-09 17:58:35 +01:00
Yuval Peress
690134356c i2c_emul: Add support for CONFIG_I2C_TARGET_BUFFER_MODE
Add emulation and test to support the buffered target mode.

Signed-off-by: Yuval Peress <peress@google.com>
2024-08-09 08:40:51 -04:00
Yuval Peress
c394b2e6f8 test: Add i2c emulation for targets
Update i2c_emul.c to support i2c_target_register and i2c_target_unregister
function calls as well as support address forwarding in emulation.
Address forwarding helps us test IPCs in native sim. Instead of having to
emulate 2 separate cores, we can forward read/write requests from one bus
to another bus (effectively creating a loop). This way the same image can
simulate both the controller and the target.

Signed-off-by: Yuval Peress <peress@google.com>
2024-08-09 08:40:51 -04:00
Armin Brauns
054cc09c88 drivers: add bindings for all existing mcp23xxx variants
This allows getting rid of the ngpios property, which is implicit in the
part number. It also prepares for configuring pins as open-drain on
supporting chips in the next commit.

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
2024-08-09 09:55:30 +02:00
Armin Brauns
75b3bf5b6c drivers: remove legacy mcp23s17 driver
This chip is handled by the more generic mcp23xxx driver, which will get a
microchip,mcp23s17 compatible binding in the next commit.

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
2024-08-09 09:55:30 +02:00
Sadik Ozer
6b41240038 soc: Add the MAX32666 SoC
Add MAX32666 Kconfig and dts files

Co-authored-by: Okan Sahin <okan.sahin@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-08-09 09:55:01 +02:00
Jason Yu
83c801965e dts: nxp,lcd-8080: Add dts binding for nxp lcd 8080 interface gpio
- Currently this interface is used by panel LCD-PAR-S035

Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
2024-08-09 09:54:51 +02:00
Ricardo Rivera-Matos
ab6a738d83 dts: haptics: Adds the DRV2605 devicetree bindings
Adds the devicetree bindings for the DRV2605 haptic driver IC.

Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
2024-08-08 15:57:12 +02:00
Jordan Yates
76d43a8f62 dts: spi: move overrun-character from Nordic to base
Move the `overrun-character` property from the common Nordic SPI
binding to the `spi-controller` base binding. This gives users of the
SPI interface a way to query what the default value is at compile-time,
and potentially avoid allocation of large constant buffers.

Signed-off-by: Jordan Yates <jordan@embeint.com>
2024-08-08 06:17:45 -04:00
Anke Xiao
878d417020 dts: arm: nxp: nxp_ke1xz.dtsi: add lpspi and dma support
Add spi and dma dts configurations information for frdm_ke17z and
frdm_ke17z512 boards.

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-08-08 06:07:51 -04:00
Richard Wheatley
edcfef92a5 drivers: pinctrl: updated to add interrupt direction
Updated to add pinctrl interrupt direction

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2024-08-08 06:06:21 -04:00
Sadik Ozer
7323757e36 soc: Add the MAX32662 SoC
Add MAX32662 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-08-07 19:04:26 -04:00
Grzegorz Swiderski
79b0154f5e dts: nordic: Remove cpu property from VPR nodes
It's a superfluous value which used to be required by tooling, but now
we can remove it.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-08-07 19:01:55 -04:00
Grzegorz Swiderski
fa2240ba31 dts: nordic: nrf54h20: Fix PPR CLIC address
Between SoC revisions, the address was moved from 0x5F909000 in the
global domain, to 0xF0000000 in PPR's private address space.

Move the corresponding DT node out of `cpuppr_vpr` range to a separate
bus node, which is considered inaccessible to all cores but `cpuppr`.
This is expressed by selectively leaving out the `simple-bus` compatible
and `ranges` property, i.e., they're only set in `nrf54h20_cpuppr.dtsi`.

This lets the interrupt controller node remain visible at system level,
for the purpose of describing IRQ mappings between cores in devicetree.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-08-07 19:01:55 -04:00
Scott Worley
a698b77fb4 dts: microchip: mec5: Base MEC5 MEC174x, MEC1752, MECH172x DTSI files
Add the base DTSI chip files for Microchip MEC174x, MEC175x,
and MECH172x using new MEC5 HAL.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2024-08-07 07:18:09 -04:00
Jonathan Rico
36c9fdcb85 boards: Add support for 01space esp32c3 0.42 oled
From https://github.com/01Space/ESP32-C3-0.42LCD/

Adapted from the XIAO ESP32C3 board.

Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
2024-08-07 07:17:54 -04:00
Maochen Wang
5583518c78 dts: arm: nxp_rw6xx: add imu interrupts
Add imu and wakeup done interrupts.

Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
2024-08-07 07:17:23 -04:00
Maochen Wang
0495d890b5 dts: wifi: add nxp wifi device tree compatible
Add nxp wifi device tree yaml file.

Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
2024-08-07 07:17:23 -04:00
Felipe Neves
af91d06b00 drivers: mbox: mbox_esp32: add support for esp32 MBOX driver
as an alternative for IPM driver.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
2024-08-07 07:17:01 -04:00
Duy Phuong Hoang. Nguyen
0c93268e52 driver: clock: Update clock control driver for RA8
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-07 07:16:45 -04:00
Yiding Jia
eb351436ad drivers: pinctrl: rp2040: oe-override option
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.

RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.


Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
2024-08-07 07:16:28 -04:00
Sadik Ozer
a055587721 soc: Add the MAX32675 SoC
Add MAX32675 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-08-06 17:18:02 -04:00
Tahsin Mutlugun
910d88741a dts: arm: adi: Add MAX32680 DMA instance and binding file
Add DMA0 node to MAX32680 dtsi file and add binding file for DMA slots.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
2024-08-06 17:16:35 -04:00
Furkan Akkiz
b64c0b829a dts: arm: adi: Add MAX32672 DMA instance and binding file
Add DMA0 node to MAX32672 dtsi file and add binding file for DMA slots.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
2024-08-06 17:16:35 -04:00
Mert Ekren
fd52e38aef dts: arm: adi: Add MAX32670 DMA instance and binding file
Add DMA0 node to MAX32670 dtsi file and add binding file for DMA slots.

Signed-off-by: Mert Ekren <mert.ekren@analog.com>
2024-08-06 17:16:35 -04:00
Furkan Akkiz
53cb59cfc4 dts: arm: adi: Add MAX32690 DMA instance and binding file
Add DMA0 node to MAX32690 dtsi file and add binding file for DMA slots.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
2024-08-06 17:16:35 -04:00
Sadik Ozer
def2dcb70b dts: arm: adi: max32: Add MAX32 DMA driver bindings
Add MAX32 DMA driver bindings and DMA instance for MAX32655 MCU.

Co-authored-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-08-06 17:16:35 -04:00
Gerard Marull-Paretas
009f3e3669 dts: riscv: nordic: nrf54h20: introduce cpuflpr
Add a new base devicetree file for the FLPR core.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
c2ddba98a0 dts: nordic: nrf54h20: define cpuflpr VEVIF TX instance
Define the FLPR VEVIF instance (used to send _tasks_).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d8c84309e0 dts: nordic: nrf54h20: define cpuflpr VEVIF RX instance
Define the FLPR VEVIF instance (used to receive _tasks_).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d77ee01d10 dts: nordic: nrf54h20: define FLPR CLIC instance
Define the FLPR CLIC instance.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
b5522411e3 dts: nordic: nrf54h20: define cpuflpr_vpr coprocessor
Add a new entry for the FLPR co-processor instance.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d3ab37ceab dts: nordic: nrf54h20: define cpuflpr
Define the FLPR VPR CPU instance.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
0e93eb3ad1 dts: bindings: pinctrl: nrf: add nordic,clock-enable
On new SoCs, certain pins need to enable the clock setting on the pin
for it to work properly. For now, this has been handled internally in
the pinctrl driver, however, it appears to be an instance-specific
property (e.g. UARTE/SPIM instances in the fast domain do not require
such setting). Move the configuration of this settings to DT, the best
place where to have instance-specific hardware settings.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
7c011741fa dts: nordic: nrf54h20: set clocks for uart120 instance
UARTE120 is clocked by HFSFLL120 instance.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
2552978df3 dts: nordic: nrf54h20: define hsfll120 instance
HSFLL120 is a clock used by fast peripherals, and it is controlled by
the system controller. From an application perspective, it is a fixed
clock. Note that it has multiple outputs (clk_main @ 320MHz, and
clk_main2|4 which provide the main clock divided by 2 and 4,
respectivelu). Only the main frequency is represented for now.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
a41a22f3e1 dts: bindings: clock: fixed-clock: include base.yaml
Include base.yaml, so that properties like `clocks` can be optionally
set.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
c2cbbd7238 dts: nordic: nrf54h20: fix uarte120 IRQ
It's 230, not 229.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 14:32:40 +02:00
Damian Nikodem
ed31037d5f drivers: ssp: fix program of MLCS register
Programming of the MLCS register was performed on the incorrect bits.
Additionally, saving the new version did not erase the previously set
value, which could result in an incorrect register value.

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
2024-08-06 10:28:16 +02:00
Chaitanya Tata
1d18144e64 dts: bindings: wifi: Add nRF70 Wi-Fi support
Add necessary bindings for the nRF70 Wi-Fi chips from Nordic
semiconductors ASA.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2024-08-06 10:27:21 +02:00
Gerard Marull-Paretas
d11db98d42 dts: bindings: regulator: add nordic,nrf91x-regulators
To describe nRF91X specific REGULATORS IP.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 09:17:10 +01:00
Gerard Marull-Paretas
7feacc62d1 dts: arm: nordic: nrf5340: instantiate regulators
Instantiate all available regulators: VREGMAIN, VREGRADIO and VREGH.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 09:17:10 +01:00
Gerard Marull-Paretas
e5e01a7f33 dts: bindings: regulator: add nordic,nrf53x-regulator-hv
nRF53X HV regulator differs from eg nRF52X as it offers a silent mode
option. For this reason, a new compatible is used, even if now such
capability is not exposed yet.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 09:17:10 +01:00
Gerard Marull-Paretas
8d6695030f dts: bindings: regulator: add nordic,nrf53x-regulators
nRF53X regulator IP is specific to that series, eg, not equal to nRF91X.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-06 09:17:10 +01:00