This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
This adds an architecture-specific post processing after memory
writes. This introduction is due to GDB's behavior regarding
breakpoints in code. GDB may choose to write break instructions
instead of using hardware breakpoints to interrupt code
execution (e.g. for manual breakpoint or stepping through code).
There is no separate GDB packet type for this. So we need to
make an assumption that a memory write may be to setup break
instructions. Different architectures may have their own unique
ways of dealing with instruction cache in this situation. So we
defer to the architecture code to handle this.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This fixes GDB backtracing by forcibly spilling all registers,
and faking values for WINDOWSTART and WINDOWBASE. This is
effectively telling GDB that only A0-A3 and AR0-AR3 contain
active data and other physical registers do not. GDB then must
rely on spilled values on stack. Otherwise, GDB will try to
look at all AR* registers for previous frame(s). Since we
do not save all AR* register values, there is nothing for GDB
to look at, and thus failing to unwind stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Inside copy_to_ctx(), we are typecasting the stack pointer into
a 32-bit array pointer, and there was unbalanced const between
two sides. Since we should not be modifying anything inside
that array, add const to the 32-bit array pointer too. So now
the compiler will not complain about discarding the const
qualifier.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The calculation of number of high registers is not entirely
correct. We need to get past the pointer to BSA in the stack
frame before reaching the high registers. The location address
difference between the BSA and start of high registers then
can be used to calculate how many high registers in the stack
frame. So correct the start location of high registers in
the calculation as it was incorrect before. Though the result
would be the same as further divisions would mask this error.
However, it is better to correct this for readability.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add an overlay in the GDB stub test for ESP-WROVER-KIT board
to enable using its UART for remote GDB communication.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
add missing break statement so that CLOCK_CONTROL_AMBIQ_TYPE_LFXTAL case
is handled correctly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
we iterate over all the channels, and if more than one channel is
active at a time. interrupt on any one of active channel was
triggering callback for other active channel, because flags value
is 1 (enabled). this is commit handle this behaviour and only
trigger callback if bits other than status is set
Signed-off-by: Anuj Pathak <anuj@croxel.com>
This patch adds a missing include directive to `spi.dtsi` in the
`build_all` configuration.The include is required because commit
2ac316465f introduced the use of `GPIO_ACTIVE_HIGH` and `GPIO_ACTIVE_LOW`
macros.
Signed-off-by: Patryk Koscik <pkoscik@antmicro.com>
Add argument to the TLS credential `cred buf` command that enables
a shell bypass to write the TLS credential directly to the credential
buffer.
This is useful for writing load credentials that cannot fit in a single
`cred buf` command and would otherwise have to be split into multiple
cred buf commands.
Sending multiple in succession like that from a script for example very
easily causes the shell RX buffer to get full, resulting in multiple
`RX ring buffer full.` warnings.
This is very difficult for a script to handle.
Using a bypass has much better performance and can easily avoid the
RX ring buffer full condition without increasing the RX ring buffer
to much.
It is also easier for a script to use.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Due to the lack of the overlays for lots of platforms, bring up the
platform_allow again before the sample ifdef are refined
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Adds a common vendor dts file specifying the default partition
layout for nRF54L05-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp_ns board targets and updates boards
to use this common file.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a workaround for partitions on nrf54l10 non-secure devices to
prevent build issues, this needs to be fixed properly when a TF-M
update is done which sets the partition sizes properly
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L10-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
When running the tests/drivers/memc/ram on the
adi_eval_adin1110ebz target, do not involve sram1, sram2
That will avoid warning about orphan section for
`DT_N_S_memory_10000000_P_zephyr_memory_region_STRING_TOKEN
and DT_N_S_memory_20040000_P_zephyr_memory_region_STRING_TOKEN
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING
value for testcase to pass for higher transfer speeds.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
jlink runner works fine for the Pico2, just like Pico1 (rpi_pico).
Copied relevant lines from rpi_pico/board.cmake.
Fixed typo in documentation.
Signed-off-by: Koen Van Herck <koen.v.herck@gmail.com>
Make the GNSS emul driver less capable w.r.t fix interval so that we can
exercise more error paths if e.g. user requests a fix interval of 100ms.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
arch_elf_relocate_global() and arch_elf_relocate_local() aren't LLEXT
API functions, they're internal implementation functions, move them
to llext_internal.h
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
With experience it becomes clear, that failing to resolve symbols
during the linking process is likely fatal for the module loading and
a simple warning isn't enough. Fail loading instead.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Functions like `add` and `sub` can only return base 10 integers, which
means they can't really be used to define Kconfig symbols of type `hex`.
For the same reason, there already exist pairs of devicetree functions
named e.g., `dt_node_reg_addr_(int|hex)` after different return types.
Introduce `add_hex`, `sub_hex`, and friends.
To avoid confusion, it should be possible for those new functions to
accept arguments in base 16 as well. It's actually easier to let all
arithmetic functions take their inputs in "any" base, by leveraging
Python's built-in: `int(..., base=0)`.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
