- Added config BT_HCI_SETUP to enable HCI vendor-specific Setup feature,
- Added pointer to 'setup' function in bt_hci_driver structure.
BT_HCI_SETUP feature is useful when the BT Controller requires execution
of the vendor-specific commands sequence to initialize the BT Controller
before the BT Host executes a Reset sequence. To enable this feature the
CONFIG_BT_HCI_SETUP should be enable.
Fixes#41140
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Address the issue mentioned in zephyrproject-rtos#7412
Using printf() with "%x" to print an off_t value produces the
following warning:
format '%x' expects 'unsigned int', argument has type 'long int'
228 | LOG_DBG("Erasing sector at 0x%08x", offset);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~
| |
| off_t {aka long int}
In newlib off_t is long. Even though both int and long are 4 bytes wide
in the architecture in use, GCC wants to see "%lx" to printf() a long.
Using "%"PRIx32 still produces the same warning because PRIx32
(from inttypes.h) still expands to simply an "x" and not "lx".
PR zephyrproject-rtos#40004 has solved this by casting offset to
ssize_t. The same solution is emulated here.
Signed-off-by: Milind Paranjpe <milind@whisper.ai>
Fixed#41945
NO_PINT_INT can have the same value as a specific pin.
E.G. For 1 byte pint_pin_int_t it equaled interrupt1.
Now is instead always 1 higher than the highest pin.
Expects fsl to keep setting values from 0 to
(number of connected outputs - 1)
Signed-off-by: Martin Koehler <koehler@metratec.com>
Turns out that xt-xcc will bail when faced with a real core-isa.h (it
wants you to rely on the builtins in the compiler). Undefine __XCC__
to force it to actually parse and emit declarations for its own
header.
(Also adds a newline to the generated one-line C file to silence a warning)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
A lot of tests need to be able to get their current tid and do some
action with it. It makes sense for the `before` function/rule to be
able to run in the same thread as the test. Note that the `after`
function does not run in the same thread because we need to guarantee
that it will run.
Signed-off-by: Yuval Peress <peress@google.com>
Fix for issue #41012 to allow compiler to treat
IRQn_Type to be more than 8-bit. This will ensure NVIC numbers
more than 127 (required for MEC172x device) will work
correctly with irq_enable() API
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
We had a similar sequence for interrupt return, where we were
selecting (actually only for the benefit of qemu) the highest priority
EPCn/EPSn registers for our RFI instruction. That works much better
in python the preprocessor.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The kernel coherence cache flush code was using a scratch register to
mark the top of the stack. Likewise a good candidate for ZSR use.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is actually Cadence-authored code, but its use of EXCSAVE1 as a
sideband input to the exception handler is very much in the same
family of tricks. Use ZSR assignments here too.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Zephyr likes to use the various Xtensa scratch registers for its own
purposes in several places. Unfortunately, owing to the
configurability of the architecture, we have to use different
registers for different platforms. This has been done so far with a
collection of different tricks, some... less elegant than others.
Put it all in one place. This is a python script that emites a
"zsr.h" header with register assignments for all the existing users.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Bug #40189 tripped over an interesting synchronization scenario that
wasn't called out in the docs. Poll signals are level triggered, and
if you're adjusting the level from a racing context (e.g. resetting it
before the next "event" from an ISR or another thread) the polling
thread might wake up but then miss the event. Mention this case
explicitly in documentation.
Fixes#40189
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Algorithm was failing in case when overflow mode was enabled
but allocation of new message failed. It could happen if message
size exceeded buffer size. Losing track of buffered messages
can lead to logging processing freeze.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Updates sched_cpu_update_usage() such that the CPU runtime stats
only update the its non-idle time when the current thread is not the
idle thread. This is necessary as otherwise the CPUs idle-time will
be double counted in k_thread_runtime_stats.execution_cycles.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
- Abstract buffer offset computation for better code clarity.
- Rework the logic around rw/ro strings to simplify the logic and
to guard against overflows even when only computing the needed buffer
size.
- Use modulus to simplify alignment tests (generated assembly is
the same).
- Avoid CBPRINTF_ prefixes for local macro names
- Better pointer types to reduce cast usage.
- Add more comments.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
* New m_can driver variant for STM32H7, as it uses the complete m_can
register set.
* Fix definitions for CAN_MCAN_RXF0S_F0FL, CAN_MCAN_TXEFC_EFSA_POS.
Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
The irq_lock() API is a legacy API not to be used for synchronization
by new code, and in any case is only being used in cargo-cult fashion
here. These test cases all do synchronous exceptions, there's
literally nothing to synchronize against.
(And in this case they're exposing a legacy wart. On platforms where:
1. SMP=y, which causes irq_lock() to be implemented as a somewhat
complicated global lock
2. No ARCH_EXCEPT() macro is defined, which causes the kernel to
use a fallback that simply aborts the current thread.
...this test will then abort a thread holding the lock, which will
cause it to be orphaned (if it weren't a legacy API, the kernel
should probably attempt to clean it up in k_thread_abort(), but it
is, and it doesn't), so the next attempt to lock it will hang.
And it's even worse, because this test builds with SMP=y and
MP_NUM_CPUS=1, so the hand will happen with interrupts masked on a
system with only one CPU, and everything will lock up solid.)
Fixes#41877
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Update the custom vector table to add the OS Event timer
interrupt which is used on RT595 as the kernel system timer
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update to add support for Flexcomm8-13.
2. Fix the clock control driver, the enclosing #define
was incorrect.
3. Identify HS_SPI port using the appropriate Register
define
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
For multicore devices like nRF53, shim layer part of setting mac keys
and frame counters is called on application core where
CONFIG_NRF_802154_ENCRYPTION is disabled (the define concerns radio
driver for net core). This commit replaces
CONFIG_NRF_802154_ENCRYPTION with CONFIG_IEEE802154_2015.
Signed-off-by: Lukasz Maciejonczyk <lukasz.maciejonczyk@nordicsemi.no>
Implement an empty `otPlatLog` function when `CONFIG_LOG` is not
enabled. This also fixes the issue with `log_count_args` not being
available when logging is disabled.
Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
DMA between a host os and processor (such as an x86 processor running
linux) and vice versa is used and supported by Intel's HDA DMA
Controller. This provides a method to transfer data, using hardware,
between the host and the local processor running Zephyr. The enums
added here are used to extend the dma_status direction enum
which provides information back to the DMA user and driver the
direction of the DMA transfer for a particular channel. This can
then be used, where needed, to add logic around the direction of the
transfer.
In addition to adding the two directions it adds enums to account for
cases where additional DMA directions that are IP and driver specific
may exist.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
We don't use TLB at the moment. Jumping to address 0 (USEG)
leads to TLB exception (instruction fetch).
Division by zero leads to TRAP exception.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.
See https://www.linux-mips.org/wiki/MIPS_Malta for details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
