drivers: can: m_can variant for STM32H7
* New m_can driver variant for STM32H7, as it uses the complete m_can register set. * Fix definitions for CAN_MCAN_RXF0S_F0FL, CAN_MCAN_TXEFC_EFSA_POS. Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
This commit is contained in:
Jeremy Wood
Anas Nashif
parent
03135f4604
commit
1caa7f6cb9
7 changed files with 365 additions and 22 deletions
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@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_CAN_MCUX_FLEXCAN can_mcux_flexcan.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_SAM can_sam.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_STM32 can_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_STM32FD can_stm32fd.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_STM32H7 can_stm32h7.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_RCAR can_rcar.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE can_handlers.c)
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@ -96,6 +96,7 @@ config CAN_AUTO_BUS_OFF_RECOVERY
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source "drivers/can/Kconfig.sam"
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source "drivers/can/Kconfig.stm32"
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source "drivers/can/Kconfig.stm32fd"
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source "drivers/can/Kconfig.stm32h7"
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source "drivers/can/Kconfig.mcux"
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source "drivers/can/Kconfig.mcp2515"
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source "drivers/can/Kconfig.mcan"
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@ -10,7 +10,8 @@ config CAN_MCAN
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help
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Enable Bosch m_can driver.
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This driver supports the Bosch m_can IP. This IP is built into the
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STM32G4, STM32G0 and the Microchip SAM controllers with CAN-FD.
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STM32G4, STM32G0, STM32H7, and the Microchip SAM controllers with
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CAN-FD.
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if CAN_MCAN
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32
drivers/can/Kconfig.stm32h7
Normal file
32
drivers/can/Kconfig.stm32h7
Normal file
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@ -0,0 +1,32 @@
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# STM32H7 FD-CAN configuration options
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# Copyright (c) 2022 Blue Clover
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_STM32_H7 := st,stm32h7-fdcan
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config CAN_STM32H7
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bool "STM32H7 FDCAN driver"
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default $(dt_compat_enabled,$(DT_COMPAT_STM32_H7))
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select CAN_MCAN
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select USE_STM32_LL_RCC
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if CAN_STM32H7
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config CAN_MAX_STD_ID_FILTER
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int "Maximum number of std ID filters"
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default 28
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range 0 28
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help
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Defines the maximum number of filters with standard ID (11-bit)
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that can be attached.
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config CAN_MAX_EXT_ID_FILTER
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int "Maximum number of ext ID filters"
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default 8
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range 0 8
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help
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Defines the maximum number of filters with extended ID (29-bit)
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that can be attached.
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endif #CAN_STM32H7
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@ -297,10 +297,14 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
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(can->crel & CAN_MCAN_CREL_DAY) >> CAN_MCAN_CREL_DAY_POS);
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#ifndef CONFIG_CAN_STM32FD
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uint32_t mrba = 0;
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#ifdef CONFIG_CAN_STM32H7
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mrba = (uint32_t)msg_ram;
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#endif
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#ifdef CONFIG_CAN_MCUX_MCAN
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uint32_t mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK;
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mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK;
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can->mrba = mrba;
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#endif
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can->sidfc = (((uint32_t)msg_ram->std_filt - mrba) & CAN_MCAN_SIDFC_FLSSA_MSK) |
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(ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
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can->xidfc = (((uint32_t)msg_ram->ext_filt - mrba) & CAN_MCAN_XIDFC_FLESA_MSK) |
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@ -312,24 +316,8 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
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can->rxbc = (((uint32_t)msg_ram->rx_buffer - mrba) & CAN_MCAN_RXBC_RBSA);
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can->txefc = (((uint32_t)msg_ram->tx_event_fifo - mrba) & CAN_MCAN_TXEFC_EFSA_MSK) |
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(ARRAY_SIZE(msg_ram->tx_event_fifo) << CAN_MCAN_TXEFC_EFS_POS);
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can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA_MSK) |
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(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
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#else /* CONFIG_CAN_MCUX_MCAN */
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can->sidfc = ((uint32_t)msg_ram->std_filt & CAN_MCAN_SIDFC_FLSSA_MSK) |
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(ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
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can->xidfc = ((uint32_t)msg_ram->ext_filt & CAN_MCAN_XIDFC_FLESA_MSK) |
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(ARRAY_SIZE(msg_ram->ext_filt) << CAN_MCAN_XIDFC_LSS_POS);
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can->rxf0c = ((uint32_t)msg_ram->rx_fifo0 & CAN_MCAN_RXF0C_F0SA) |
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(ARRAY_SIZE(msg_ram->rx_fifo0) << CAN_MCAN_RXF0C_F0S_POS);
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can->rxf1c = ((uint32_t)msg_ram->rx_fifo1 & CAN_MCAN_RXF1C_F1SA) |
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(ARRAY_SIZE(msg_ram->rx_fifo1) << CAN_MCAN_RXF1C_F1S_POS);
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can->rxbc = ((uint32_t)msg_ram->rx_buffer & CAN_MCAN_RXBC_RBSA);
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can->txefc = ((uint32_t)msg_ram->tx_event_fifo & CAN_MCAN_TXEFC_EFSA_MSK) |
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(ARRAY_SIZE(msg_ram->tx_event_fifo) <<
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CAN_MCAN_TXEFC_EFS_POS);
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can->txbc = ((uint32_t)msg_ram->tx_buffer & CAN_MCAN_TXBC_TBSA) |
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(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
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#endif /* !CONFIG_CAN_MCUX_MCAN */
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can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA) |
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(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
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if (sizeof(msg_ram->tx_buffer[0].data) <= 24) {
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can->txesc = (sizeof(msg_ram->tx_buffer[0].data) - 8) / 4;
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@ -1084,7 +1084,7 @@
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/* Rx FIFO 0 Fill Level */
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#define CAN_MCAN_RXF0S_F0FL_POS (0U)
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#define CAN_MCAN_RXF0S_F0FL_MSK (0x3FUL << CAN_MCAN_RXF0S_F0FL_POS)
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#define CAN_MCAN_RXF0S_F0FL_MSK (0x7FUL << CAN_MCAN_RXF0S_F0FL_POS)
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#define CAN_MCAN_RXF0S_F0FL CAN_MCAN_RXF0S_F0FL_MSK
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/* Rx FIFO 0 Get Index */
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#define CAN_MCAN_RXF0S_F0GI_POS (8U)
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320
drivers/can/can_stm32h7.c
Normal file
320
drivers/can/can_stm32h7.c
Normal file
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@ -0,0 +1,320 @@
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/*
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* Copyright (c) 2022 Blue Clover
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/can.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <drivers/clock_control.h>
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#include <drivers/pinctrl.h>
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#include <kernel.h>
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#include <stm32_ll_rcc.h>
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#include "can_mcan.h"
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#include <logging/log.h>
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LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT st_stm32h7_fdcan
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struct can_stm32h7_config {
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struct can_mcan_msg_sram *msg_sram;
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void (*config_irq)(void);
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struct can_mcan_config mcan_cfg;
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const struct pinctrl_dev_config *pcfg;
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struct stm32_pclken pclken;
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};
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struct can_stm32h7_data {
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struct can_mcan_data mcan_data;
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};
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static int can_stm32h7_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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ARG_UNUSED(dev);
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const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
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if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
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LOG_ERR("Can't read core clock");
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return -EIO;
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}
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*rate = rate_tmp;
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LOG_DBG("rate=%d", *rate);
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return 0;
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}
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static int can_stm32h7_get_max_filters(const struct device *dev,
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enum can_ide id_type)
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{
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ARG_UNUSED(dev);
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if (id_type == CAN_STANDARD_IDENTIFIER) {
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return NUM_STD_FILTER_DATA;
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} else {
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return NUM_EXT_FILTER_DATA;
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}
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}
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static int can_stm32h7_clock_enable(const struct device *dev)
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{
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int ret;
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const struct can_stm32h7_config *cfg = dev->config;
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const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL1Q);
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ret = clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken);
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if (ret != 0) {
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LOG_ERR("failure enabling clock");
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return ret;
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}
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if (!LL_RCC_PLL1Q_IsEnabled()) {
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LOG_ERR("PLL1Q clock must be enabled!");
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return -EIO;
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}
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return 0;
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}
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static void can_stm32h7_set_state_change_cb(const struct device *dev,
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can_state_change_callback_t cb,
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void *user_data)
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{
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struct can_stm32h7_data *data = dev->data;
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data->mcan_data.state_change_cb = cb;
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data->mcan_data.state_change_cb_data = user_data;
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}
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static int can_stm32h7_init(const struct device *dev)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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struct can_stm32h7_data *data = dev->data;
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int ret;
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret != 0) {
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LOG_ERR("CAN pinctrl setup failed (%d)", ret);
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return ret;
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}
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ret = can_stm32h7_clock_enable(dev);
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if (ret != 0) {
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return ret;
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}
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ret = can_mcan_init(dev, &cfg->mcan_cfg, cfg->msg_sram,
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&data->mcan_data);
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if (ret != 0) {
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return ret;
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}
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cfg->config_irq();
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return 0;
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}
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static enum can_state can_stm32h7_get_state(const struct device *dev,
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struct can_bus_err_cnt *err_cnt)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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return can_mcan_get_state(&cfg->mcan_cfg, err_cnt);
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}
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static int can_stm32h7_send(const struct device *dev,
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const struct zcan_frame *frame,
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k_timeout_t timeout, can_tx_callback_t callback,
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void *user_data)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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struct can_stm32h7_data *data = dev->data;
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return can_mcan_send(&cfg->mcan_cfg, &data->mcan_data, cfg->msg_sram,
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frame, timeout, callback, user_data);
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}
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static int can_stm32h7_add_rx_filter(const struct device *dev,
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can_rx_callback_t callback,
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void *user_data,
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const struct zcan_filter *filter)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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struct can_stm32h7_data *data = dev->data;
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return can_mcan_add_rx_filter(&data->mcan_data, cfg->msg_sram,
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callback, user_data, filter);
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}
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static void can_stm32h7_remove_rx_filter(const struct device *dev,
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int filter_id)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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struct can_stm32h7_data *data = dev->data;
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can_mcan_remove_rx_filter(&data->mcan_data, cfg->msg_sram, filter_id);
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}
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static int can_stm32h7_set_mode(const struct device *dev, enum can_mode mode)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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return can_mcan_set_mode(&cfg->mcan_cfg, mode);
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}
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static int can_stm32h7_set_timing(const struct device *dev,
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const struct can_timing *timing,
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const struct can_timing *timing_data)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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return can_mcan_set_timing(&cfg->mcan_cfg, timing, timing_data);
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}
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static void can_stm32h7_line_0_isr(const struct device *dev)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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struct can_stm32h7_data *data = dev->data;
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can_mcan_line_0_isr(&cfg->mcan_cfg, cfg->msg_sram, &data->mcan_data);
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}
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static void can_stm32h7_line_1_isr(const struct device *dev)
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{
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const struct can_stm32h7_config *cfg = dev->config;
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struct can_stm32h7_data *data = dev->data;
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can_mcan_line_1_isr(&cfg->mcan_cfg, cfg->msg_sram, &data->mcan_data);
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}
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static const struct can_driver_api can_api_funcs = {
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.set_mode = can_stm32h7_set_mode,
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.set_timing = can_stm32h7_set_timing,
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.send = can_stm32h7_send,
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.add_rx_filter = can_stm32h7_add_rx_filter,
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.remove_rx_filter = can_stm32h7_remove_rx_filter,
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.get_state = can_stm32h7_get_state,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif
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.get_core_clock = can_stm32h7_get_core_clock,
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.get_max_filters = can_stm32h7_get_max_filters,
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.set_state_change_callback = can_stm32h7_set_state_change_cb,
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/* Timing limits are per the STM32H7 Reference Manual (RM0433 Rev 7),
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* section 56.5.7, FDCAN nominal bit timing and prescaler register
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* (FDCAN_NBTP).
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*/
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.timing_min = {
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.sjw = 0x00,
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.prop_seg = 0x00,
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.phase_seg1 = 0x00,
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.phase_seg2 = 0x00,
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.prescaler = 0x00
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},
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.timing_max = {
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.sjw = 0x7f,
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.prop_seg = 0x00,
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.phase_seg1 = 0x100,
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.phase_seg2 = 0x80,
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.prescaler = 0x200
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},
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#ifdef CONFIG_CAN_FD_MODE
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/* Data timing limits are per the STM32H7 Reference Manual
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* (RM0433 Rev 7), section 56.5.3, FDCAN data bit timing and prescaler
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* register (FDCAN_DBTP).
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*/
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.timing_min_data = {
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.sjw = 0x00,
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.prop_seg = 0x00,
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.phase_seg1 = 0x00,
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.phase_seg2 = 0x00,
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.prescaler = 0x00
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},
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.timing_max_data = {
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.sjw = 0x10,
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.prop_seg = 0x00,
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.phase_seg1 = 0x20,
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.phase_seg2 = 0x10,
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.prescaler = 0x20
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}
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#endif
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};
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#ifdef CONFIG_CAN_FD_MODE
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#define CAN_STM32H7_MCAN_MCAN_INIT(n) \
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{ \
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.can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \
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.bus_speed = DT_INST_PROP(n, bus_speed), \
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.sjw = DT_INST_PROP(n, sjw), \
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.sample_point = DT_INST_PROP_OR(n, sample_point, 0), \
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.prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \
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DT_INST_PROP_OR(n, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \
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.bus_speed_data = DT_INST_PROP(n, bus_speed_data), \
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.sjw_data = DT_INST_PROP(n, sjw_data), \
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.sample_point_data = \
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DT_INST_PROP_OR(n, sample_point_data, 0), \
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.prop_ts1_data = DT_INST_PROP_OR(n, prop_seg_data, 0) + \
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DT_INST_PROP_OR(n, phase_seg1_data, 0), \
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.ts2_data = DT_INST_PROP_OR(n, phase_seg2_data, 0), \
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.tx_delay_comp_offset = \
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DT_INST_PROP(n, tx_delay_comp_offset) \
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}
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#else /* CONFIG_CAN_FD_MODE */
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#define CAN_STM32H7_MCAN_MCAN_INIT(n) \
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{ \
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||||
.can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \
|
||||
.bus_speed = DT_INST_PROP(n, bus_speed), \
|
||||
.sjw = DT_INST_PROP(n, sjw), \
|
||||
.sample_point = DT_INST_PROP_OR(n, sample_point, 0), \
|
||||
.prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \
|
||||
DT_INST_PROP_OR(n, phase_seg1, 0), \
|
||||
.ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \
|
||||
}
|
||||
#endif /* !CONFIG_CAN_FD_MODE */
|
||||
|
||||
#define CAN_STM32H7_MCAN_INIT(n) \
|
||||
static void stm32h7_mcan_irq_config_##n(void); \
|
||||
\
|
||||
PINCTRL_DT_INST_DEFINE(n); \
|
||||
\
|
||||
static const struct can_stm32h7_config can_stm32h7_cfg_##n = { \
|
||||
.msg_sram = (struct can_mcan_msg_sram *) \
|
||||
DT_INST_REG_ADDR_BY_NAME(n, message_ram), \
|
||||
.config_irq = stm32h7_mcan_irq_config_##n, \
|
||||
.mcan_cfg = CAN_STM32H7_MCAN_MCAN_INIT(n), \
|
||||
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
||||
.pclken = { \
|
||||
.enr = DT_INST_CLOCKS_CELL(n, bits), \
|
||||
.bus = DT_INST_CLOCKS_CELL(n, bus), \
|
||||
}, \
|
||||
}; \
|
||||
\
|
||||
static struct can_stm32h7_data can_stm32h7_dev_data_##n; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(n, &can_stm32h7_init, NULL, \
|
||||
&can_stm32h7_dev_data_##n, \
|
||||
&can_stm32h7_cfg_##n, \
|
||||
POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
|
||||
&can_api_funcs); \
|
||||
\
|
||||
static void stm32h7_mcan_irq_config_##n(void) \
|
||||
{ \
|
||||
LOG_DBG("Enable CAN inst" #n " IRQ"); \
|
||||
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, line_0, irq), \
|
||||
DT_INST_IRQ_BY_NAME(n, line_0, priority), \
|
||||
can_stm32h7_line_0_isr, DEVICE_DT_INST_GET(n), 0); \
|
||||
irq_enable(DT_INST_IRQ_BY_NAME(n, line_0, irq)); \
|
||||
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, line_1, irq), \
|
||||
DT_INST_IRQ_BY_NAME(n, line_1, priority), \
|
||||
can_stm32h7_line_1_isr, DEVICE_DT_INST_GET(n), 0); \
|
||||
irq_enable(DT_INST_IRQ_BY_NAME(n, line_1, irq)); \
|
||||
}
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(CAN_STM32H7_MCAN_INIT)
|
||||
Loading…
Add table
Add a link
Reference in a new issue