Add pin control support to gpio_imx driver, so that GPIO pin muxes will
be selected when the use configures a pin as GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add additional pin controller settings for iMX application core SOCs, as
well as a "fallback" pin control setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control group definitions for all iMX application cores. This
commit does not enable pin control for any iMX cores, as the SOC level
support is not present, but does define the require pin mux settings for
all boards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This builtin gcc function is not available in xcc compiler.
Adding a memory compiler barrier as it is done in compiler_barrier.
compiler_barrier() and __sync_synchronize() are not the same, the
former is a sw barrier while the latter can be a hw barrier
like (mfence/sfence) in X86.
I didn't find anything equivalent for xtensa so just implementing a
SW barrier.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This add a new sample application to test and validate
the stm32 octospi driver on the NOR octo-flash present on
stm32 disco kits
There should be a special case to erase the complete flash.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit enables the octo SPI peripheral to the flash-nor
on the target board b_u585i_iot02a from STMicroelectronics.
Note that JESD16 requires 9 dwords for the sdfp table.
The configuration is for OctoSPI bus through IO manager.
The NOR octoflash is MX25LM51245 or compatible.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit enables the octo SPI peripheral to the flash-nor
on the target board stm32l562e_dk from STMicroelectronics.
Note that JESD16 requires 9 dwords for the sdfp table.
The NOR octoflash is MX25LM51245 or compatible.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Simplifies the driver and Gives a generic function to prepare the Regular
commands for each instruction.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the stm32 octospi driver based on the exisitng quadspi
for stm32 devices and source code from the STM32Cube.
This drivers initialized the peripheral and the NOR memory
in SPI or OctoSPI mode with STR or DTR data Transfer rates.
The NOR-flash can provide the SDFP table directly (if supported)
or through the DeviceTree.
Limitation: no DMA transfer.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With the introduction of the OSPI NOR flash controller
more octal commands and parameters are defined.
It completes the existing SPI commands
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The new octoSPI flash controller driver
requires parameter to configure the peripheral
especially matching the data mode and the transfer rate
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the DTS binding for OCTOSPI interface for the stm32 devices
from STMicroelectronics.
This corresponds to a NOR octo SPI flash.
In this config, there is only on NOR-flash device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Whenever EC bootloader already configured a pin as output and
high, any further reconfiguration via pinctrl driver causes a
glitch in said pin with current sequence.
Defer pin direction configuration to be last operation over
gpio control register to avoid the glitch.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Log a message when the modem asynchronously closes a link. This is
useful information to the user as it can explain the root cause of later
failures.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This commit fixes the test message showing an incorrect input value of
-1 when the actual input value is 1234.56789.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The test test_mode_size_str_with_strings() is defined but was not
added to the test suite, so it never ran before. Add this to
the suite so this can be tested.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the missing "@param package_flags" for
z_log_msg2_runtime_create() and z_log_msg2_runtime_vcreate().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx eSPI and host_subs driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx adc driver. Please notice users need to
configure the corresponding pinctrl nodes in 'pinctrl-0' property in the
adc0 DT node. For example, if ADC0 and ADC2 channels are selected for
the application, please add the follwoings in your board DT layout file.
&adc0 {
status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45
&adc0_chan2_gp43>;
pinctrl-names = "default";
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx tachometer driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in ps2 driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in pwm driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in i2c driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in uart driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Increase the heap size for RT1170 EVK to allocate the
display buffers for a 720x1280 display
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Add MIPI support on MXRT1170 EVK board
2. To support the 720x1280 on RT1170 EVK, we
require more heap for the display buffers.
Increase the heap size via HEAP_MEM_POOL_SIZE config
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Update the MCUX ELCDIF driver to use CONFIG_MCUX_ELCDIF_POOL_BLOCK_NUM
for the number for frame buffers to allocate.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Adding LOG_BACKEND_MOCK_OUTPUT_DEFAULT &
LOG_BACKEND_MOCK_OUTPUT_SYST to UNDEF_KCONFIG_WHITELIST as Kconfig
options generated by a template under testcases are not
identified by Compliance check by default.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
Adding testcases for mipi syst logging format. Excluding
problem architectures from the testcase as SYS-T does not
support 64-bit or big endian architectures. The posix arch
is excluded as it generates numerous anomalous runtime messages
because it does not have the means to determine when data
resides in the rodata section.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
mps2_an521 and mps3_an547 need yet more time with TFM 1.6 to pass their
tests. This change was recomended by RajKumar Kanagaraj. Thanks!
Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org>
