In RISCV, stack always grows by a multiple of 16 bytes, even if we are saving
data of size < 16 bytes onto the stack.
Hence, for riscv32 architecture a bigger stack size is required for
test_mpool_concept, otherwise we experience stack overflow.
Change-Id: I938aa511efcae66f0131fa1bc23bd68600421885
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
When trying to build with newlib we get:
hci_driver.c: In function 'hci_driver_open':
hci_driver.c:389:10:
error: format '%d' expects argument of type 'int', but argument 2 has
type 'uint32_t {aka long unsigned int}' [-Werror=format=]
BT_ERR("Required RAM size: %d, supplied: %u.", err,
^
This is because we have different types for {u}int32_t between newlib
and mini-libc. We have to decide how we are going to handle this going
forward. Various options include use of PRIu32, making mini-libc match
newlib's types, disabling the -Werror=format, etc.
Change-Id: I5df8fa05dd7658e1f6b2eeb8fa84e3270f3dd208
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
"struct k_mbox_msg mmsg" should be initialized before using.
"int" value returned by k_mem_pool_alloc() should be checked.
Coverity-CID: 160083
Coverity-CID: 160470
Change-Id: I35714bf9d76723c5fdd8c2963bf76b42ae1b1867
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
assert should not contain "i++" which might work differently in a non-debug
build.
Coverity-CID: 160469
Change-Id: Id8fd50127dd93de1676b812ac0888c9ec2e1b5de
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
"int" value returned by k_mem_pool_alloc() should be checked.
Coverity-CID: 160471
Change-Id: I7ec19147e7a51997fed890075b06eba30bef9126
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
This patch changes Quark SE power drivers to support multicore scenarios
e.g. both LMT and ARC core are enabled and manage power.
Handling LPS states in multicore scenarios are dead simple because LPS
states are core-specific states. It means that putting the LMT core in
LPS doesn't affect the ARC core, and vice-versa. DEEP_SLEEP state, on
the other hand, affects both cores since it turns power off from the SoC
and both cores are shutdown. It means that if LMT puts the system in
DEEP_SLEEP, ARC core is shutdown even if it is busy handling some task.
In order to support the multicore scenario, this patch introduces the
SYS_POWER_STATE_DEEP_SLEEP_2 state to both ARC and x86 power drivers.
On ARC, this state works as following:
1) Save ARC execution context;
2) Raise a flag to inform the x86 core that ARC is ready to enter in
DEEP_SLEEP;
3) Enter in the lowest core-specific power state, which in this case is
LPSS.
On x86, DEEP_SLEEP_2 is very similar to DEEP_SLEEP. The difference relies
in the post_ops() which calls _arc_init() in order to start ARC core so
it can restore its context.
This patch also adds the test/power/multicore/ directory which provides
sample application to x86 and ARC cores in order to easily verify the
multicore support. In test/power/multicore/README.rst you can find more
details regarding the applications.
Jira: ZEP-1103
Change-Id: Ie28ba6d193ea0e58fca69d38f8d3c38ca259a9ef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
"ret" returned from k_msgq_put() should be checked.
Coverity-CID: 160084
Change-Id: I192db3a67ab9489e8338f6636d4c2a6935e98d74
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.
Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
The K_<thread option> flags/options avaialble to users were hidden in
the kernel private header files: move them to include/kernel.h to
publicize them.
Also, to avoid any future confusion, rename the k_thread.execution_flags
field to user_options.
Change-Id: I65a6fd5e9e78d4ccf783f3304b607a1e6956aeac
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Convert testcases to use the CMSIS NVIC APIs or direct NVIC register
access rather than the internal ones so we can remove them in the future.
Change-Id: I2a5a3eae713e66944cf105e7fffa603b88522681
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
_NvicSwInterruptTrigger is only utilized by a testcase for irq handling
on ARM-V7M. Just put the code into the testcase so we dont need to
support an additional interface.
Change-Id: I763c63c32a7a52918250458351d08b8fa54069dd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some new tests were added that had the Apache 2.0 boilerplate licensing
instead of the SPDX licensing tag.
Change-Id: I4bde8c9c6e7a6d44bceeffb6bbcff9f62d417648
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
It is useful that the user API can know whether the connection
was established properly or not. So this commit adds status
parameter to connect callback in net_context API.
The call to connect callback needs to be set properly in TCP
code. This commit does not fix the connect callback call which
is not properly done right now in net_context.c.
Change-Id: I284a60ddd658ceef9e65022e96591f467a936a09
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If the prefix length % 8 is not 0, then the remaining
bit length was calculated incorrectly and the prefixes
were claimed to match even though they might not be the
same.
Adding a test cases for testing this properly.
Coverity-CID: 157591
Change-Id: I9cb5a73d5cc211ec183176400fa5e2dfd209e2da
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
- Introduce NET_LINK_ADDR_MAX_LENGTH which is either 6 or 8
depending on whether CONFIG_NET_L2_IEEE802154 is used
- Instead of being a placeholder single index array of uint8_t,
let's use NET_LINK_ADDR_MAX_LENGTH to assign the size of the
"addr" array field in the net_linkaddr_storage structure.
- Now that the "addr" field of net_linkaddr_storage contains the
true size of the link address, we can remove "storage" field
which was hard coded to 8 bytes (2 uint32_t's).
- Fix 2 references to the "storage" field of the net_linkaddr_storage
structure.
Change-Id: I2ea12058280b289f65085964eb7d503d4fd260c2
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Add kernel pipe test cases which cover basic pipe apis usage
across thread and isr
Change-Id: I11899411b305535297f2e25056678d5b7df8fb95
Signed-off-by: jing wang <jing.j.wang@intel.com>
Add fifo/fifo test cases with unified kernel, which cover
basic apis across differnt contexts - thread and isr
Change-Id: Icb61d3dcd564167b0bd70419c652e0b000869959
Signed-off-by: jing wang <jing.j.wang@intel.com>
TestPurpose: verify memory pool concepts.
All TESTPOINTs extracted from kernel documentation.
https://www.zephyrproject.org/doc/kernel/memory/pools.html#concepts
ZEP-1210
Change-Id: I6250e4c26ddf361e74a76c23082cfdb376705560
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
TestPurpose: verify memory pool APIs.
All TESTPOINTs extracted from kernel-doc comments in <kernel.h>
ZEP-1210
Change-Id: I7dcc0638e7b9c4d6b5ffe282e4fe41ca520d003f
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
TestPurpose: verify API thread safe in multi-threads environment.
Thread safe test is explained with more details here:
https://gerrit.zephyrproject.org/r/#/c/9464/7/ test_mpool_threadsafe.c
Please comment if you think it necessary as an extensive kernel test.
Jira: ZEP-1209
Change-Id: I52a7ff393d72785622c047289e7d92286e131cc7
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
TestPurpose: verify memory pool concepts.
All TESTPOINTs extracted from kernel documentation.
https://www.zephyrproject.org/doc/kernel/memory/slabs.html#concepts
ZEP-1209
Change-Id: I95c6cd666212218b9928356f9439e67a2fcf9b73
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
TestPurpose: verify memory slab APIs.
All TESTPOINTs extracted from kernel-doc comments in <kernel.h>
ZEP-1209
Change-Id: I80bc85e96110e7106b3fc5883b982d71c6a7e50b
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
tests/kernel/mem_slab --> tests/kernel/mem_slab/test_mslab
For the purpose to hold other mslab test apps.
Jira: ZEP-1209
Change-Id: I4a72b02a0a5095bb7cfbf73396b6d003ea63f92e
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Coverity was warning about an array overrun that should never happen.
Add an extra check to verify that is indeed the case.
Coverity issue 152017.
Change-Id: Ie6269acaa85387ba051dbff87b4bfaab860517a6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Having TX buffers split into numerous pools has the downside of
increased memory consumption. This patch takes the initial step to
consolidate these pools into a single one, saving about 248 bytes of
RAM for a basic configuration.
Change-Id: I449ba18b44a9a6af68e9a2c44f19a9286eb88b14
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I2faa823226cd76d129d2bc3db961c9b862aaf784
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I43a5c5112d694efdc14c5a0bcb4cafdc196d2680
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The commit verify below PWM apis
pwm_pin_set_cycles()
pwm_pin_set_usec
test PWM apis under always-on, half-on and alway-off modes
Change-Id: I2251be23ad9c443703dac44e138651a63d2d7211
Signed-off-by: jing wang <jing.j.wang@intel.com>
Precursor patches have arranged that conditional compilation hanging
on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the
config variable to reflect this.
Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Merges the ksdk pinmux dev driver into the regular ksdk pinmux driver,
which now exposes the public pinmux API. Removes the private ksdk pinmux
API and converts the frdm_k64f and hexiwear_k64 boards to use the public
pinmux API.
Jira: ZEP-958, ZEP-1432
Change-Id: Ie5f60b604133093050b9c596050cad776d7b7cb3
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
A few CONFIG options got set twice in sensors_n_z.conf, remove the
duplicates as we get warnings associated with this:
warning: override: reassigning to symbol GPIO
warning: override: reassigning to symbol SENSOR
warning: override: reassigning to symbol SPI
warning: override: reassigning to symbol SYS_LOG_SENSOR_LEVEL
Change-Id: I7a723218db8e365bdb45c004e93bd2c4f55ab5ac
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This will replace the current goal of 'make qemu' with 'make run' and
moves Qemu handling into its own file and into the boards instead of
being architecture specific.
We should be able to add new boards that support some other type of
emulation (by adding scripts/Makefile.<emu type>) and allow the board to
define their own options for the use type of emulation.
'make qemu' will still work, however it will be deprecated, starting
with this commit it is recommended to use 'make run'.
Jira: ZEP-359
Change-Id: I1cacd56b4ec09421a58cf5d010e22e9035214df6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
These samples/tests fail to build on some of the nRF5x platforms. We
don't need Bluetooth enabled for these tests so we can reduce footprint
by turning it off.
Change-Id: I87e62a1d70f80d2bc22414d6a9e591e36ad9fa06
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
RAM size has increased on arduino_101_ble which causes it to no longer
be able to build test_controller_dbg.
Change-Id: Iab8ed2857db23d048cfa6b04e2d1fea31efbb13c
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some thread fields were 32-bit wide, when they are not even close to
using that full range of values. They are instead changed to 8-bit fields.
- prio can fit in one byte, limiting the priorities range to -128 to 127
- recursive scheduler locking can be limited to 255; a rollover results
most probably from a logic error
- flags are split into execution flags and thread states; 8 bits is
enough for each of them currently, with at worst two states and four
flags to spare (on x86, on other archs, there are six flags to spare)
Doing this saves 8 bytes per stack. It also sets up an incoming
enhancement when checking if the current thread is preemptible on
interrupt exit.
Change-Id: Ieb5321a5b99f99173b0605dd4a193c3bc7ddabf4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Add global option for legacy configurations and enable by default for
backward compatibility. Disable option on tests and keep it on legacy
samples and tests.
Jira: ZEP-964
Change-Id: I0831e2aa74d438b1ac74eb762186cb220a504beb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Disk IO functions are used by both FS and USB Mass Storage.
This patch refactors those from FS directory to a separate one.
In addition existing, config options were modified to make
stuff meaningful.
Jira: ZEP-1276
Change-Id: Ia2a2e18f3dbbbdb964c3dc0427d8138ad86134cd
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
