Commit graph

9175 commits

Author SHA1 Message Date
Andrzej Głąbek
cb86a2b306 drivers: i2c_nrfx_twim: Fix handling of zero-length transfers
For a zero-length transfer, the STOP task is not triggered
automatically by the shortcut with the event that signals
the transfer end because such event is not generated.
Trigger this task "manually" to prevent the driver getting
stuck after the address byte is acknowledged.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2021-04-26 13:41:41 +02:00
Eduardo Montoya
8ff12f3ace net: openthread: enable CSL delayed transmissions
Add support for delayed transmission of frames for the CSL
Transmitter OpenThread function.

Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
2021-04-26 13:40:43 +02:00
Sylvio Alves
fe621f7071 wifi: esp32: allow wifi symbols into flash
When BT and WiFi coexists, IRAM usage increases a lot.
Add configuration that allow wifi symbols
to be placed in flash, freeing space in IRAM.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-04-26 13:39:21 +02:00
Mulin Chao
1a2e59b2e9 driver: wdt: npcx: replace critical sections with timeout mechanism.
TWDT0 is loaded with a new value and the counter restarts counting with
it by written RST bit in Timer Control register (T0CSR) to 1. Then, the
RST bit in T0CSR register is cleared automatically on the 2nd rising
edge of T0IN clock. Since TWCP is set to 1:32, the maximum time that RST
bit is unset is 32 * (1 / 32768) ~= 980us.

Polling this bit within a critical section in current npcx watchdog
driver isn't a good approach since it might block the other interrupts
need to service them in time. This CL introduces a timeout mechanism and
removes the critical section to improve this disadvantage. Consider the
clock tolerance, 2 ms is a suitable timeout value for RST bit. We also
remove polling for WD_RUN bit in T0CSR. Npcx watchdog needs serval LFCLK
(32k Hz) clocks to stop watchdog. 1 ms is long enough for the timeout
mechanism.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-23 15:03:15 -05:00
Krishna Mohan Dani
5de1b09cc0 drivers/flash: STM32: Adding condition to enable HSI clock for L1 series.
This commit adds changes to enable HSI clock for stm32l1 series.

Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
2021-04-23 14:59:06 +02:00
Krishna Mohan Dani
3374bc128a drivers/flash: STM32: Getting clock settings from DT.
This commit uses DT APIs to get the flash clock settings.

Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
2021-04-23 14:59:06 +02:00
Hake Huang
b609242903 dma: add request channel and release channel helper
add two dma api for dynamic channel reqest and release

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2021-04-23 14:58:40 +02:00
Dino Li
0ab51ff657 drivers: gpio: ite_it8xxx2: enable more gpio groups
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.

This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
2021-04-23 06:31:56 -04:00
Mulin Chao
f16f37f86a driver: pwm: npcx: Add output open drain support
NPCX PWM supports output buffet select to push-pull or open-drain. Add
output buffer select option 'drive-open-drain' in devicetree for NPCX
PWM. If set, the PWM output will be configured as open-drain. If not
set, defaults to push-pull.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-04-22 18:03:38 -04:00
Mulin Chao
440d9dc5d4 driver: itim: npcx: check ITEN bit to prevent return fake error.
During polling ITEN bit to make sure ITIM timer is enabled, we might
have the chance that npcx_itim_evt_enable() return fake error when
timeout expired but ITEN bit is set already if CONFIG_ZERO_LATENCY_IRQS
is enabled. (Since SVCall's interrupt priority is not the highest, the
other interrupts with IRQ_ZERO_LATENCY flag could preempt CPU resource
at this moment.)

In order to prevent return fake error code, this CL adjusts the check
conditions for ITEN bit and timeout.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-22 18:03:06 -04:00
Wealian Liao
abb94b1198 soc: power: npcx: Clear host access IRQ pending bit before enabling
NPCX host access IRQ enables before entering deep sleep. The pending
bit lets chip wake up from sleep immediately. Clear host access IRQ
pending bit before enabling.

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-04-22 18:02:36 -04:00
Johan Hedberg
9e9a990ba0 drivers: uart_ns16550: Fix naming for struct uart_ns16550_dev_data_t
Rename uart_ns16550_dev_data_t to uart_ns16550_dev_data since it's not a
typedef.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-04-22 15:30:24 -05:00
Johan Hedberg
baecd7e55a drivers: uart_ns16550: Remove CMake-based templating
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-04-22 15:30:24 -05:00
Johan Hedberg
8cfa5deb16 drivers: uart_ns16550: Remove support for hard-coded PCIe interrupts
There are no boards that need hard-coded interrupts so just remove this
build-time conditional branch. The way going forward is that all PCIe
devices should always use PCIE_IRQ_DETECT.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-04-22 15:30:24 -05:00
Kumar Gala
e1032ad2c3 include: Move emul.h to drivers/emul.h
Move emul.h out of the top level include/ dir into
include/drivers/emul.h and deprecated the old location.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-04-22 12:51:01 -04:00
Sidhdharth Yadav
e2a29bf6a4 drivers: pwm: Adding a flag to allow build for stm32l1 series
Include a flag to allow build for stm32l1 series

Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
2021-04-22 11:29:34 +02:00
Julien Massot
d86c61fd57 drivers: gpio: add Renesas RCar gpio
Add GPIO controller driver that can be found on Renesas
RCar gen3 soc series.

Controller can handle up to 32 GPIOs per banks.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Julien Massot
20fdb6cbfb drivers: timer: add R-Car cmt driver
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Julien Massot
2ad6e4e376 drivers: clock_control: add R-Car CPG MSSR driver
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.

MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.

CPG registers allow to get the rate or to set some divider like for
the CAN clock.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Armando Visconti
8717654c1d drivers/sensor: iis2iclx: move ctx structure inside config
Move ctx structure from struct data to struct config, so that
it can be filled at compile time and we could get rid of the bus
init routines.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2021-04-21 20:41:46 -04:00
Armando Visconti
6fa0d01c5f drivers/sensor: iis2iclx: Use DT helper for gpio_drdy
Use gpio_dt_spec structure and populate it using GPIO_DT_SPEC_GET
macro.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2021-04-21 20:41:46 -04:00
Johan Hedberg
776fbf2d26 drivers: i2c_dw: Remove CMake-based templating
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-04-21 20:40:52 -04:00
Johan Hedberg
3cdb5c76dd drivers: i2c_dw: Remove support for hard-coded PCIe interrupts
There are no boards that need hard-coded interrupts so just remove this
build-time conditional branch. The way going forward is that all PCIe
devices should always use PCIE_IRQ_DETECT.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-04-21 20:40:52 -04:00
Mahesh Mahadevan
243d6a2ed1 drivers: timer: Add MCUX OS timer
Add OS timer for the MCUX SoC's

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-04-21 20:40:24 -04:00
Yong Cong Sin
084a8b6bf4 drivers: modem: BG9X wait for RDY instead of polling AT.
BG9X wait for RDY instead of polling AT.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2021-04-21 17:04:40 +03:00
Jiafei Pan
460a962b87 interrupt_controller: gic: distribute interrupts to cpu listed in dts
We only need to distribute interrupts to CPU Cores with the count
of CONFIG_MP_NUM_CPUS, and get Core's MPID from CPU nodes in dts.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-21 09:02:50 -04:00
Johann Tael
5425700e74 drivers: modem: ublox-sara-r4: add TLS offload support
Currently it's able to connect to google iot. All other use cases are
untested.

Signed-off-by: Johann Tael <jntael@gmail.com>
2021-04-21 11:13:34 +03:00
Martí Bolívar
15f9ae0e0b dts: nrf: revert i2c sda-gpios, scl-gpios changes
These changes turn out to have been incompatible with the way pinctrl
drivers are going to work, so we need to go back to what we had before
until we can agree on a better approach.

Squash of the following reverts:

Revert "boards: nrf: fix deprecated I2C properties"

This reverts commit 2a4ac9ac02.

Revert "samples: switch nrf overlays to sda-gpios, scl-gpios"

This reverts commit 01bb08e7d8.

Revert "boards: nrf: switch to sda-gpios, scl-gpios"

This reverts commit 17a66304c4.

Revert "i2c: nordic: switch to phandle arrays for pinmux"

This reverts commit 821c03a14a.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-04-20 18:32:04 +02:00
Johann Fischer
583334b606 drivers: usb_dc_nrfx: clear endpoint flags during ep_disable()
If a loaded endpoint was disabled and then reconfigured,
it is not possible to start an IN transfer and
usb_dc_ep_write() returns -EAGAIN.

Call ep_ctx_reset() to clear endpoint operations flags
and reset buffer after endpoint is disabled.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-04-20 15:04:47 +02:00
Francois Ramu
bce0d52664 drivers: flash: stm32wb: Flush caches after erase
This commit fixes sporadic kernel panics when writing big data chunks
to the flash. (data bus errors). Just like the stm32g4 does.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-04-20 12:44:14 +02:00
Francois Ramu
3620f3fcee drivers: flash: stm32g0: Flush caches after erase
This commit fixes sporadic kernel panics when writing big data chunks
to the flash. (data bus errors). Just like the stm32g4 does
but on instruction cache.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-04-20 12:44:14 +02:00
Frank Li
42333dc282 driver: usdhc: add option to disable 1.8v
When 1.8V is disabled, sdhc can only
communicate at low speed. But this can
save the external circuit for switching
between 3.3V and 1.8V, which is very
practical in costdown scenarios.

Signed-off-by: Frank Li <lgl88911@163.com>
2021-04-19 08:25:55 -05:00
Peter Bigot
67808279fb drivers: flash: spi_nor: support devices that default to protect blocks
Some SPI NOR devices, particularly Atmel and SST, power-up with block
protect bits set in the status register.  These bits must be cleared
before any erase or program operation can succeed.  However, blindly
clearing bits in SR is wrong as some of these are non-volatile and
control chip behavior, including quad-enable.

Add a devicetree flag to identify device-specific BP bits in the status
register that should be cleared on startup only for devices that need
them, and when set do the clear during initialization.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-16 12:23:06 +02:00
Peter Bigot
060204a6ae drivers: flash: spi_nor: document caller requirements
Add the standard note to two functions that require the caller to have
first acquired the device.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-16 12:23:06 +02:00
Peter Bigot
01fbe40fd4 drivers: flash: spi_nor: clean up ready detection
Reads would wait until the device was ready before issuing the first
command; writes and erases did not.  Fix this documenting and changing
so that wait-for-ready is invoked only where needed, i.e. to confirm
that a WRITE_STATUS, ERASE, or PROGRAM operation has completed before
proceeding to allow more commands to be submitted.  This matches Linux
spi_nor driver behavior.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-16 12:23:06 +02:00
Armando Visconti
2846283f84 drivers/sensor: iis2mdc: (FIX) Remove SPI Full Duplex mode
The IIS2MDC sensor does not support the SPI 4 wires. So, remove
it from the driver.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2021-04-16 12:21:11 +02:00
Armando Visconti
4df7af583a drivers/sensor: iis2mdc: Add multi-instance support
Make this driver multi-instance and use the new API.
This commit makes use of the new helpers introduced in #30536.

In particular:
    - get bus devices with DEVICE_DT_GET
    - get SPI information with SPI_CONFIG_DT_INST
    - get drdy gpios with GPIO_DT_SPEC_GET

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2021-04-16 12:21:11 +02:00
Johann Fischer
b142a47f73 drivers: regulator: enable driver when compatible node is defined
Add regulator compatibility string to Kconfig.fixed file
and allow fixed regulator driver to be enabled when compatible
node is defined. However, remove this option from common Kconfig
as it is legitimate to enable/disable regulator support.

Change menuconfig REGULATOR_FIXED to config since this
menu nesting is not necessary.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-04-16 09:45:35 +02:00
Pieter De Gendt
3ee5f427e6 drivers: flash: mcux flexspi nor: copy data to RAM buffer on write
This feature prevents issues when trying to write data to the flash
device that is located on or addressed at the same flash device.

An example is the mcuboot logic that writes a magic number to
the secondary partition header.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-04-15 16:26:39 -05:00
Pieter De Gendt
bd67c2375f drivers: flash: mcux flexspi nor: Fix write if size > SPI_NOR_PAGE_SIZE
This fixes a bug in the write function of the MCUX FlexSPI flash driver
if the length of the data is larger than a single page.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-04-15 16:26:39 -05:00
Pieter De Gendt
add98e766a drivers: flash: Support i.MX FlexSPI NOR driver with XIP
This change allows writing to the flash while running in XIP mode,
and enables mcuboot or NVS settings to be used on i.MX RT socs.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-04-15 16:26:39 -05:00
Peter Bigot
2ac596b91a usb: conversion of k_work API
Replace all existing deprecated API with the recommended alternative.

Be aware that this does not address architectural errors in the use
of the work API.

Fixes #34092

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-04-15 12:29:34 -04:00
Peng Li
e28b7e04e2 driver: serial: fixed the buffer underflow issue when clearing the port.
Set DLAB bit before reading RDR to avoid buffer underflow.

Signed-off-by: Peng Li <lipengit@gmail.com>
2021-04-15 17:19:12 +02:00
Dominik Ermel
eb37fd0b30 drivers/flash_simulator: Rename FLASH() macro to MOCK_FLASH()
The change is done to avoid redefinition errors while attempting
to enable flash_simulator with stm32 platform (stm32f4_disco)
which exports its own definition of FLASH macro, from stm32f407xx.h.
Unfortunately the stm32 definition is visible within flash_simulator
via inclusion of device.h.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2021-04-15 17:15:34 +02:00
Robert Lubos
a586f5818c drivers: ieee802154_nrf5: Remove unnecessary NULL pointer check
After changes in commit a42d6c98d3, the
pkt can no longer be a NULL pointer. Remove the unnecessary NULL pointer
check to silence the Coverity.

Coverity ID: 219536
Fixes #32912

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-04-15 14:45:50 +03:00
Sergey Ustinov
73db443320 drivers: can: can_mcp2515: fix BRP bits value
Fixes #33978.
8b6c1bd commit set 'presacaler' in BRP(Baud Rate Prescaler) bits.
It's wrong, because these bits from CNF1 register use 'prescaler - 1'.
MCP2515(DS20001801J) datasheet 'REGISTER 5-1: CNF1: CONFIGURATION
REGISTER 1 (ADDRESS: 2Ah)'.

Signed-off-by: Sergey Ustinov <originalustinov@gmail.com>
2021-04-15 12:25:23 +02:00
Kumar Gala
b55ad01898 drivers: gpio: mcux: Set pin mux config to GPIO
Set the PCR[MUX] field to kPORT_MuxAsGpio as part of configuring a GPIO
pin.  This removes the need to explicitly call pinmux_pin_set() in board
code.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-04-15 12:25:05 +02:00
Arvin Farahmand
835b875c17 drivers: ethernet: eth_sam_gmac: allow changing mac address
Support setting MAC address manually at runtime for Atmel SAM Ethernet
driver. The MAC address can be set using an ethernet management
request, e.g. (`net_mgmt(NET_REQUEST_ETHERNET_SET_MAC_ADDRESS, ...)`).

Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
2021-04-15 10:43:21 +03:00
Francois Ramu
962d6b1082 drivers: serial: uart_stm32 converted to use the new kwork API.
The structure is now k_work_delayable.
The init function is now k_work_init_delayable.
The submit function is now the k_work_reschedule.
The cancel function is now the k_work_cancel_delayable.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-04-14 18:21:33 +02:00
Shlomi Vaknin
95143fc98e drivers: dma: stm32: add support for stm32h7
Add the missing parts for adding support
to stm32h7 dma driver.
The fix is to make dmamux driver work with
dma v1 driver.

Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
2021-04-14 18:18:12 +02:00